Teledyne LeCroy QPHY-DDR3 - Manual (Page 15)

QPHY-DDR3 Software Option
917717 Rev C
15
WRITE Burst Operation
During a READ or WRITE command, DDR3 supports BC4 and BL8 on the fly using address A12 during
the READ or WRITE (AUTO PRECHARGE can be enabled or disabled).
• A12 = 0, BC4 (BC4 = burst chop, tCCD = 4).
• A12 = 1, BL8.
• A12 is used only for burst length control, not as a column address.
Figure 7. Write Timing Definition and Parameters [JESD79-3D Figure 43]