Teledyne LeCroy QPHY-DDR3 - Manual (Page 42)

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917717 Rev C
tDSS, DQS Falling Edge to CK Setup Time
Time from DQS falling edge at VREF level to CK rising edge at VREF level, see Figure 22.
tDSH, DQS Falling Edge Hold Time from CK
Time from CK rising edge at VREF level to DQS falling edge at VREF level, see Figure 22.
tDS(base), DQ and DM Input Setup Time
Input waveform timing tDS with differential data strobe enabled, is referenced from the input signal
crossing at the VIH(ac)min level to the differential data strobe crosspoint at VREF for a rising signal, and
from the input signal crossing at the VIL(ac)max level to the differential data strobe crosspoint at VREF for
a falling signal applied to the device under test
DQS and DQS# signals must be monotonic between VIL(dc)max and VIH(dc)min.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VREF(dc) and the first crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined
as the slew rate between the last crossing of VREF(dc) and the first crossing of VIL(ac)max.
JESD79-3D Tables 73 and 74 explain the limit compensation versus the slewrate of the measured
signals. Timing limits are initially specified for input slewrate of 1V/ns for single-ended signals and 2V/ns
for differential signal (for DQS and CK).
tDH(base), DQ and DM Input Hold Time
Input waveform timing tDH with differential data strobe enabled, is referenced from the differential data
strobe crosspoint at VREF to the input signal crossing at the VIH(dc)min level for a falling signal and from
the differential data strobe crosspoint at VREF to the input signal crossing at the VIL(dc)max level for a
rising signal applied to the device under test
DQS and DQS# signals must be monotonic between VIL(dc)max and VIH(dc)min.
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VIL(dc)max and the first crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined
as the slew rate between the last crossing of VIH(dc)min and the first crossing of VREF(dc).
JESD79-3D Tables 43 and 44 explain the limit compensation versus the slewrate of the measured
signals. Timing limits are initially specified for input slewrate of 1V/ns for single-ended signals and 2V/ns
for differential signal (for DQS and CK).
Four Probe tests measurements using ADDR/CTL
tIS /tIH (base) - Address and Control Input Setup Time (Hold Time)
Input waveform timing is referenced from the input signal crossing at the VIH(ac)min level to the
differential clock crosspoint at VREF for a rising signal, and from the input signal crossing at the
VIL(ac)max level to the differential clock crosspoint at VREF for a falling signal applied to the device
under test. See Figure 23 below.