Teledyne LeCroy QPHY-DDR3 - Manual (Page 35)

QPHY-DDR3 Software Option
917717 Rev C
35
tCL(avg), Average Low Pulse Width
tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses.
tCH(abs), Absolute High Pulse Width
tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the
following falling edge.
tCL(abs), Absolute Low Pulse Width
tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the
following rising edge.
tJIT(duty), Half Period Jitter
tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter over 200 consecutive cycles.
tCH jitter is the largest deviation of any single tCH from tCH(avg).
tCL jitter is the largest deviation of any single tCL from tCL(avg).
tJIT(duty) = Min/max of {tJIT(CH), tJIT(CL)}
where,
tJIT(CH) = {tCHi - tCH(avg) where i=1 to 200}
tJIT(CL) = {tCLi - tCL(avg) where i=1 to 200}
tJIT(per), Clock Period Jitter
tJIT(per) is defined as the largest deviation of any signal tCK from tCK(avg).
tJIT(per) = Min/max of {tCKi - tCK(avg) where i = 1 to 200}.
tJIT(per) defines the single period jitter when the DLL is already locked.
tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.
tJIT(per) and tJIT(per,lck) are not subject to production test.
tJIT(cc), Cycle to Cycle Period Jitter
tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles.
tJIT(cc) = Max of |{tCKi +1 - tCKi}|.
tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.
tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.
tJIT(cc) and tJIT(cc,lck) are not subject to production test.