Advanced settings, Clock period per screen division, Number of cycles for clock test – Teledyne LeCroy QPHY-DDR3 User Manual

Page 32: Max. number of samples per clock period, Configuration specific variables, Xx channel gain, Xx channel index, Xx channel invert, Xx channel offset, Speed bin paramters

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32

917717 Rev C

Advanced Settings

Clock Period per Screen Division

Oscilloscope timebase and sampling rate is set to acquire the given number of clock cycle per display
horizontal division at a given DUT Speed Grad in MT/s and for a Max. Number of Samples Per Clock
Period
. The default is 3341 clock periods (this gives a 10us/div timebase at 667 MT/s and 3.3MS max for
100 samples per period).

Timebase = [Clock Period Per Screen Division] / ([DUT Speed Grade in MT/s] / 2 * 1e6)

Maximum Samples = [Max. Number Of Samples Per Clock Period] * [Clock Period Per Screen
Division]
* 10

Number of cycles for Clock test

Jedec standard requires 200 cycles for the Clock compliance test.

This is the default value of this variable. Any positive number can be entered.

Max. Number Of Samples Per Clock Period

The oscilloscope timebase and sampling rate is set to acquire the given number of points per clock
period. The oscilloscope is always set to at least acquire at 20GS/s. Also, if an oscilloscope with greater
than 6GHz bandwidth is used, the bandwidth is limited to 6GHz. See the Clock Period Per Screen
Division
topic for more details. Choose between 10;20;50;100;200;500 or 1000. The default value is 100.

Configuration Specific Variables

The following variables are specific to the configuration in which they appear under. Some of these
variables appear under multiple configurations.

XX Channel Gain

Allows the user to manually specify the vertical scale in V/div for XX SUT. XX can be Clock, DQ, DQS,
DQSn, ADD/CTRL, or DM. The default is 0 for auto-scale.

XX Channel Index

Allows the user to manually specify the channel XX SUT. XX can be Clock, DQ, DQS, DQSn, ADD/CTRL,
or DM. Default is 1 for CK, 2 for DQS, 3 for DQ and 4 for others

XX Channel Invert

Allows the user to invert XX SUT. XX can be Clock, DQ, DQS, DQSn, ADD/CTRL, or DM. The default is
False.

XX Channel Offset

Allows the user to manually specify the offset in Volts for XX SUT. XX can be Clock, DQ, DQS, DQSn,
ADD/CTRL, or DM. The default is 0 for auto-scale.

Speed Bin Paramters

CAS Latency
Allows the user to specify the CAS Latency (CL) used to define tCK(avg) limits (see tables 61 to 64 in
JEDEC Standard).

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