IEI Integration PICOe-GM45A - Manual (Page 37)

PICOe-GM45A Half-Size CPU Card
Page 37
2.5.3 Intel
®
ICH9M Low Pin Count (LPC) Interface
The ICH9M LPC interface complies with the LPC 1.1 specifications. The LPC bus from the
ICH9M is connected to the Super I/O chipset.
2.5.4 Intel
®
ICH9M PCI Interface
The PCI interface on the ICH9M is compliant with the PCI Revision 2.3 implementation.
Some of the features of the PCI interface are listed below.
PCI Revision 2.3 compliant
33 MHz
5V tolerant PCI signals (except PME#)
Integrated PCI arbiter supports up to seven PCI bus masters
The PCI bus is connected to an interface gold finger on the bottom of the CPU card and
supports up to four expansion PCI cards on the backplane.
Figure 2-9: PCI Golden Finger