2 s/pdif rx/tx interface control (cir = 0001h), Cs4207 – Cirrus Logic CS4207 User Manual

Page 130

Advertising
background image

130

DS880F4

CS4207

6.15.6.2 S/PDIF RX/TX Interface Control (CIR = 0001h)

Bits

Type

Default

Description

15

Read Only

0b

Reserved

14

Read/Write

0b

TX 2 Enable: Routes S/PDIF Transmitter 2 to
the GPIO1/DMIC_SDA2/SPDIF_OUT2 pin.
0 - The pin functions as GPIO1 or DMIC_SDA2,
according to

DMIC2 Enable.

1 - The pin functions as SPDIF_OUT2, regard-
less of

DMIC2 Enable.

13

Read/Write

0b

Reserved

12

Read/Write

0b

TX 2 Raw Data Mode: Enables AES3 Direct
Mode. In this mode, a direct copy of the received
NRZ data from the HD Audio bus is sent to
S/PDIF transmitter 2.
0 - Normal S/PDIF TX 2 Data Mode.
1 - Enable Raw S/PDIF TX 2 Data Mode.

11

Read/Write

0b

RX To TX 2 Loopthru: This bit is used to enable
an internal loop through from the S/PDIF RX to
S/PDIF TX 2. The path is a straight digital mux
from input to output. No re-clocking is performed.
0 - Do not loop S/PDIF RX to S/PDIF TX 2.
1 - Enable S/PDIF RX to S/PDIF TX 2 loopthru.

10

Read/Write

0b

RX A/B Chnl Status Select: Specifies the chan-
nel from which to extract the channel status bits.
‘0’b - Select channel A status.
‘1’b - Select channel B status.

9:8

Read/Write

00b

Reserved

7

Read/Write

0b

TX 1 Raw Data Mode: Enables AES3 Direct
Mode. In this mode, a direct copy of the received
NRZ data from the HD Audio bus is sent to
S/PDIF transmitter 1.
0 - Normal S/PDIF TX 1 Data Mode.
1 - Enable Raw S/PDIF TX 1 Data Mode.

6

Read/Write

0b

RX Raw Data Mode: Enables AES3 Direct
Mode. In this mode, a direct copy of the received
NRZ data from the S/PDIF receiver including the
C, U, and V bits are transmitted to the HD Audio
bus. The time slot occupied by the Z bit is used
to indicate the location of the block start.
0 - Normal S/PDIF RX Data Mode.
1 - Enable Raw S/PDIF RX Data Mode.

5

Read/Write

0b

RX To TX 1 Loopthru: This bit is used to enable
an internal loop through from the S/PDIF RX to
S/PDIF TX 1. The path is a straight digital mux
from input to output. No re-clocking is performed.
0 - Do not loop S/PDIF RX to S/PDIF TX 1.
1 - Enable S/PDIF RX to S/PDIF TX 1 loopthru.

Advertising