Cirrus Logic CS4207 - Manual (Page 8)

8 DS880F4
CS4207
1. PIN DESCRIPTIONS
1.1 CS4207 48-pin QFN Pinout:
Pin Name QFN Pin Description
VL_IF 1
Digital Interface Signal Level (Input) - Digital supply for the GPIO, S/PDIF and Digital Mic inter-
faces. Refer to the Recommended Operating Conditions for appropriate voltages.
GPIO0/
DMIC_SDA1
2
General Purpose I/O (Input/Output) - General purpose input or output line, or
Digital Mic Data Input (Input) - The first data input line from a digital microphone.
VL_HD 3
Digital Interface Signal Level (Input) - Digital supply for the HD Audio interface. Refer to the
Recommended Operating Conditions for appropriate voltages.
DMIC_SCL 4
Digital Mic Clock (Output) - The high speed clock output to the digital microphone.
SDO 5
Serial Data Input (Input) - Serial data input stream from the HD Audio Bus.
BITCLK 6
Bit Clock (Input) - 24 MHz bit clock from the HD Audio Bus.
DGND 7
Digital Ground (Input) - Ground reference for the internal digital section.
SDI 8
Serial Data Output (Input/Output) - Serial data output stream to the HD Audio Bus.
VD 9
Digital Power (Input) - Positive power for the internal digital section.
SYNC 10
Sync Clock (Input) - 48 kHz sync clock from the HD Audio Bus.
HPREF
Thermal Pad
14 13
8
7
6
5
4
3
2
1
15 16 17 18 19 20
29
30
31
32
33
34
35
36
41 42 43 44 45 46 47 48 37 38 39 40
12
11
10
9
21 22 23 24
25
26
27
28
SPDIF_OUT1
SENSE
_A
VL_IF LINEOUT_R1+
Top-Down (Through Package) View
48-Pin QFN Package
LINEOUT_L1+
LINEOUT_L1-
LINEOUT_R2-
LINEOUT_R2+
LINEOUT_L2+
LINEOUT_L2-
VBIAS (DAC)
VCOM
VREF+ (ADC)
AGND
VA
SPDIF_IN FL
YN
FL
YC
VHP_FILT- FLYP HPO
U
T_L
HPREF HPO
U
T_R
VA_HP LI
NEO
U
T_
R
1-
GPIO0/DMIC_SDA1
VL_HD
DMIC_SCL
SDO
BITCLK
DGND
SDI
VD
SYNC
RESET#
GPIO1/DMIC_SDA2
/SPDIF_OUT2
MICBIAS MI
CIN
_L
-
MICIN_
L+
MIC
IN_R+ GPI
O
2
GPI
O
3
MICIN_R-
LI
NEIN
_L
+
LINEIN_C-
LINEIN_R+
VA_REF
VHP_FILT+
HPGND