Cirrus Logic CS4207 - Manual (Page 33)

DS880F4 33
CS4207
6. HD AUDIO CODEC SUPPORTED VERBS AND RESPONSES
6.1 Software Programming Model
Figure 10. Software Programming Model
Headphone
Single-Ended
Jack Detect A
D0/D3 Power States
DAC1
PCM;
Vol/Mute;
D0/D 3 Power States
02h
HD_Audio
Bus
Line O ut 1
SE/Balanced
Jack Detect D
D0/D3 Power States
DAC2
PCM;
Vol/Mute;
D0/D 3 Power States
03h
09h
0Ah
Line O ut 2
SE/Balanced
(Speaker)
DAC3
PCM;
Vol/Mute;
D0/D 3 Power States
04h 0Bh
Line In 1/Mic In 2
SE/Pseudo-Diff; Boost
Jack Detect C
D0/D3 Power States
ADC1
PCM;
Vol/Mute;
D0/D 3 Power States
05h 0Ch
M ic In 1/Line In 2
SE/PSD/Bal; Boost
Vref; Jack Detect B
D0/D3 Power States
ADC2
PCM;
Vol/Mute;
D0/D 3 Power States
06h 0Dh
Digital M ic In 1
Boost
0Eh
S/PDIF Receiver
Lock/Unlock Detect
D0/D3 Power States
S/PDIF IN
PCM /Non-PCM ;
D0/D 3 Power States
07h 0Fh
S/PDIF Transm itter 1
S/PDIF OUT 1
PCM /Non-PCM ;
D0/D 3 Power States
08h 10h
G PIO
01h
Jack Sense
Processing
W idget
11h
Digital M ic In 2
Boost
12h
Beep
G enerator
13h
S/PDIF Transm itter 2
S/PDIF OUT 2
PCM /Non-PCM ;
D0/D 3 Power States
14h 15h