Cirrus Logic CS4270 - Manual (Page 21)

DS686F1 21
CS4270
could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multi-
channel system. In Stand-Alone Mode, the high-pass filter is always active and continuously subtracts a
measure of the DC offset from the output of the decimation filter.
5.1.7 Mode Selection & De-Emphasis
The sample rate, Fs, can be adjusted from 4 kHz to 216 kHz and De-emphasis, optimized for 44.1 kHz,
is available in Single-Speed Mode. In Stand-Alone Master Mode, the CS4270 must be set to the proper
mode via the mode pins, M1 and M0. In Slave Mode, the CS4270 auto-detects Speed Mode and the M0
pin becomes De-emphasis select. Stand-alone definitions of the mode pins in Master Mode are shown in
Table 5 .
5.1.8 Access to Serial Audio Interface Format
Either I²S or Left-Justified serial audio data format may be selected in Stand-Alone Mode. To use the I 2 S
format, tie the I²S/LJ pin to VLC during power up. To use LJ format, tie I²S/LJ to DGND during power up.
5.2 Serial Control Port Mode
5.2.1 Access to Serial Control Port Mode
Reliable power-up is achieved by keeping the device in reset until the power supplies, clocks, and config-
uration pins are stable. It is also recommended that RST be asserted if the analog or digital supplies drop
below the minimum specified operating voltages to prevent power glitch related issues.
After RST is released, the device is put into Serial Control Port Mode by setting the power down bit
through a SPI or I²C transaction, as described in
Section 6.1 and Section 6.2 .
If the transaction is not completed within 1,045 sample periods after the release of reset, the device enters
Stand-Alone Mode.
If the first Serial Control Port transaction is ongoing while the device is executing pop control, there is a
chance of generating audio transients. The details of the duration of pop control is outlined in
Section 5.3.1
“Power-Up” on page 24 .
When the device is Serial Control Port Mode, it can be programmed as desired. After clearing the power-
down bit, desired device functioning can start.
5.2.2 Access to Master/Slave Mode
The CS4270 supports operation in either Master Mode or Slave Mode.
• In Master Mode, LRCK and SCLK are outputs and are synchronously generated by the device. LRCK
is equal to Fs and SCLK is equal to 64x Fs.
• In Slave Mode, LRCK and SCLK are inputs, requiring external generation that is synchronous to MCLK.
It is recommended that SCLK be 48x or 64x Fs to maximize system performance.
Mode 1 Mode 0 Mode Sample Rate (Fs) De-Emphasis
0 0 Single-Speed 4 kHz - 54 kHz Off
0 1 Single-Speed 4 kHz - 54 kHz 44.1 kHz
1 0 Double-Speed 50 kHz - 108 kHz Off
1 1 Quad-Speed 100 kHz - 216 kHz Off
Table 5. CS4270 Stand-Alone Mode Control