Cirrus Logic CS4270 - Manual (Page 24)

24 DS686F1
CS4270
5.2.8 Oversampling Modes
The CS4270 operates in one of three oversampling modes based on the input sample rate. Mode selec-
tion is determined by the FM bits in the Mode Control Register (03h). Single-Speed Mode supports input
sample rates from 4 to 54 kHz and uses a 128x oversampling ratio. Double-Speed Mode supports input
sample rates from 50 to 108 kHz and uses an oversampling ratio of 64x. Quad-Speed Mode supports in-
put sample rates from 100 to 216 kHz and uses an oversampling ratio of 32x. See
Table 7 on page 22 .
5.3 Popguard Transient Control
The CS4270 uses a novel technique to minimize the effects of output transients during power-up and power-
down. This technology, when used with external DC-blocking capacitors in series with the audio outputs,
minimizes the audio transients commonly produced by single-ended single-supply converters. The Pop-
guard Transient Control
is activated inside the DAC when RST is toggled and requires no other external
control, aside from choosing the appropriate DC-blocking capacitor. See Section 8.3.3 for information about
configuration.
5.3.1 Power-Up
When the device is initially powered-up, the audio outputs, AOUTA and AOUTB, are clamped to
AGND.Following a delay of 1,045 sample periods, each output begins to ramp toward the quiescent volt-
age. Approximately 0.4 seconds later, the outputs reach VQ
and audio output begins.This gradual voltage
ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, minimizing
audible power-up transients.
5.3.2 Power-Down
To prevent audible transients at power-down, the device must first enter its power-down state. When this
occurs, audio output ceases and the internal output buffers are disconnected from AOUTA and AOUTB.
In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly dis-
charge. Once this charge is dissipated, the power to the device may be turned off and the system is ready
for the next power-on.
5.3.3 Discharge Time
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge be-
fore turning on the power or exiting the power-down state. If full discharge does not occur, a transient will
occur when the audio outputs are initially clamped to AGND. The time that the device must remain in the
power-down state is related to the value of the DC-blocking capacitance and the output load. For example,
with a 3.3
F capacitor, the minimum power-down time will be approximately 0.4 seconds.
5.4 De-Emphasis Filter (Single-Speed Mode Only)
The CS4270 includes a digital de-emphasis filter. Figure 14 shows the de-emphasis curve for Fs equal to
44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in
sample rate, Fs. Please see
Section 5.1.7 for the desired de-emphasis control for Stand-Alone Mode and
Section 5.2 for Serial Control Port Mode.
The de-emphasis feature is included to accommodate audio recordings that use 50/15 s pre-emphasis
equalization as a means of noise reduction.