5 transition control - address 05h, 1 dac single volume (bit 7), 2 soft ramp and zero cross enable (bits 6:5) – Cirrus Logic CS4270 User Manual
Page 35: Table 13. soft cross or zero cross mode selection, 3 invert signal polarity (bits 4:1), P 35, Cs4270

DS686F1
35
CS4270
8.5
Transition Control - Address 05h
8.5.1
DAC Single Volume (Bit 7)
Function:
The AOUTA and AOUTB volume levels are independently controlled by the DAC Channel A & B Volume
Control Registers when this bit is cleared.
The volumes on AOUTA and AOUTB are locked together and determined by the DAC Channel A Volume
Control Register (07h) when this bit is set.
8.5.2
Soft Ramp and Zero Cross Enable (Bits 6:5)
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
See
Zero Cross Enable
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-
out period between 512 and 1,024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or mut-
ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1,024 sample periods (10.7 ms to 21.3 ms at 48 kHz sam-
ple rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel. See
8.5.3
Invert Signal Polarity (Bits 4:1)
Function:
When set, this bit activates an inversion of the signal polarity for the appropriate channel. This is useful if
a board layout error has occurred or in other situations where a 180
phase shift is desirable.
7
6
5
4
3
2
1
0
DAC_SNGL_
VOL
DAC_SOFT
DAC_ZC
ADC_INV_
CHB
ADC_INV_
CHA
DAC_INV_
CHB
DAC_INV_
CHA
DE_EMPH
DAC_SOFT DAC_ZC
Mode
0
0
Changes take effect immediately
0
1
Zero Cross enabled
1
0
Soft Ramp enabled
1
1
Soft Ramp and Zero Cross enabled (default)
Table 13. Soft Cross or Zero Cross Mode Selection