Pin descriptions, 1 software mode – Cirrus Logic CS4270 User Manual

Page 4

Advertising
background image

4

DS686F1

CS4270

1. PIN DESCRIPTIONS

1.1

Software Mode

Pin Name #

Pin Description

SDIN

1 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

LRCK

2

Left Right Clock (Input/Output) - Determines which channel, left or right, is currently active on the serial audio
data line. The frequency of the left/right clock must be at the audio sample rate, Fs.

MCLK

3 Master Clock (Input) - Clock for the delta-sigma modulator and the digital filters.

SCLK

4 Serial Bit Clock (Input/Output) - Serial bit clock for the serial audio interface.

VD

5 Digital Power (Input) - Positive power for the digital section.

DGND

6 Digital Ground (Input) - Ground reference for the digital section.

SDOUT

7 Serial Audio Data Output (Output) - Output for two’s complement serial audio data.

VLC

8 Serial Control Port Power (Input) - Positive power for the Serial Control Port.

SDA/CDOUT 9 Serial Control Data (Input/Output) - SDA is a data I/O line in I²C Mode. CDOUT is the output data line for the

Serial Control Port in SPI format.

SCL/CCLK

10 Serial Control Port Clock (Input) - SCL is the serial input Clock for the Serial Control Port in I²C format. CCLK

is the serial input Clock for the Serial Control Port in SPI format.

AD0/CS

11 Address Bit 0 (I²C)/Serial Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C format.

CS is the chip select signal for SPI format.

AD1/CDIN

12

Address Bit 1 (I²C)/Serial Control Data (Input) - AD1 is a chip address pin in I²C Mode. CDIN is the input
data line for the Serial Control Port in SPI

format.

AD2

13 Address Bit 2 (I²C) (Input) - AD2 is a chip address pin in I²C format.

RST

14

Reset (Input) - Input for resetting all internal registers to their default settings and for placing the device in a
low-power mode.

AINA
AINB

15
16

Analog Audio Input (Input) - Analog inputs to the ADC.

VQ

17 Quiescent Voltage (Output) - Filter connection for the internal quiescent voltage.

FILT+

18 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

VA

19 Analog Power (Input) - Positive power for the analog section.

AGND

20 Analog Ground (Input) - Ground reference for the analog section.

MUTEA
MUTEB

21
24

Mute Control (Output) - Mute control signal used to control the state of the optional external analog muting
circuitry. See

Section 5.6 on page 27

.

AOUTA
AOUTB

22
23

Analog Audio Output (Output) - Analog outputs from the DAC.

1
2
3
4
5
6
7
8

21

22

23

24

9
10
11
12

17

18

19

20

13

14

15

16

SDIN

LRCK

MCLK

SCLK

VD

DGND

SDOUT

VLC

SDA/CDOUT

SCL/CCLK

AD0/CS

AD1/CDIN

MUTEB
AOUTB
AOUTA
MUTEA
AGND
VA
FILT+
VQ
AINB
AINA
RST
AD2

Advertising