Cirrus Logic CS42L52 - Manual (Page 25)

DS680F2 25
CS42L52
3/1/13
4.2 Analog Inputs
Referenced Control Register Location
Analog Front End
PDN_PGAx .........................
PGAxVOL[5:0].....................
ADCB=A ..............................
ANLGSFTx ..........................
ANLGZCx ............................
ADCxSEL[2:0] .....................
PGAxSEL5,4,3,2,1 ..............
BIASLVL[2:0] .......................
PDN_BIAS...........................
PDN_ADCx .........................
PDN_CHRG ........................
INV_ADCx ...........................
HPFRZx...............................
HPFx ...................................
HPFx_CF[1:0]......................
ADCxOVFL..........................
Digital Volume
ADCxMUTE.........................
ADCxVOL............................
ALCx....................................
ALCxSRDIS.........................
ALCxZCDIS.........................
ALCARATE[5:0]...................
ALCRRATE[5:0] ..................
MAX[2:0]..............................
MIN[2:0]...............................
NGALL.................................
NG .......................................
THRESH[3:0].......................
NGDELAY[1:0] ....................
Miscellaneous
DIGSUM[1:0] .......................
DIGMUX ..............................
“Power Down PGAx” on page 42
“PGAx Volume” on page 56
“Analog Front-End Volume Setting B=A” on page 50
“Ch. x Analog Soft Ramp” on page 49
“Ch. x Analog Zero Cross” on page 49
“ADC Input Select” on page 48
“PGA Input Mapping” on page 49
“MIC Bias Level” on page 48
“Power Down MIC Bias” on page 43
“Power Down ADCx” on page 43
“Power Down ADC Charge Pump” on page 42
“Invert ADC Signal Polarity” on page 51
“ADCx High-Pass Filter Freeze” on page 49
“ADCx High-Pass Filter” on page 49
“HPF x Corner Frequency” on page 50
“ADCx Overflow (Read Only)” on page 71
“ADC Mute” on page 51
“ADCx Volume” on page 57
“ALCx Enable” on page 67
“ALCx Soft Ramp Disable” on page 55
“ALCx Zero Cross Disable” on page 56
“ALC Attack Rate” on page 67
“ALC Release Rate” on page 68
“ALC Maximum Threshold” on page 68
“ALC Minimum Threshold” on page 69
“Noise Gate All Channels” on page 69
“Noise Gate Enable” on page 69
“Noise Gate Threshold and Boost” on page 70
“Noise Gate Delay Timing” on page 70
“Digital Sum” on page 50
“Digital MUX” on page 50
`
AIN4A/ M IC1+/
M IC2A
Gain Adjust
ALC
PDN_PGAA
PGAAVOL[5:0]
ADCB=A
ANLGSFTA
ANLGZCA
HPFRZA
HPFA
HPFA_CF[1:0] PD N_ADCA
INV_ADCA
PD N_CHRG
ALCB
ALCBSRDIS
ALCBZC DIS
MICBIAS
BIASLVL[2:0]
PDN_BIAS
P
C
M
S
e
ri
a
l In
te
rf
a
c
e
TO DSP Engine
ALCARATE[5:0]
ALC RRATE[5:0]
MAX[2:0]
M IN[2:0]
ALCA
ALCASRDIS
ALCAZC DIS
AIN1A
AIN2A
= PGAASEL[5:1]
ADC
PDN_PGAB
PGABVOL[5:0]
ADCB=A
ANLGSFTB
ANLGZCB
ADCBM UTE
DIGSFT
DIGZC
ADCBVOL[7:0]
+24/-96dB
1dB steps
HPFRZB
HPB
HPFB_CF[1:0] PDN_ADCB
INV_AD CB
PDN_CH RG
Noise Gate
N GALL
N G
THRESH[3:0]
N GDELAY[1:0]
Gain Adjust
FROM DSP ENGINE
DIGM IX
AIN3A/M IC1-/
MIC1A
AIN4B/ M IC2+/
MIC2B
AIN1B
AIN2B
AIN3B/M IC2-/
MIC1B
ANALOG PASS TH RU TO
HEADPHONE AM PLIFIER M UX
Swap/
M ix
DIGSUM [1:0]
ADCAMU TE
DIGSFT
DIGZC
ADCAVOL[7:0]
+24/-96dB
1dB steps
Refer to
“M IC Inputs”
ADC

ADCASEL[2:0]
ADCBSEL[2:0]
= PGABSEL[5:1]
Refer to
“M IC Inputs”

Figure 5. Analog Input Signal Flow