Cirrus Logic CS42L52 - Manual (Page 37)

DS680F2 37
CS42L52
3/1/13
4.9 Recommended Power-up Sequence
1. Hold RESET low until the power supplies are stable.
2. Bring RESET high.
3. The default state of the PDN bit is 1. Load the desired register settings while keeping the PDN bit set
to 11.
4. Load the required initialization settings listed in Section 4.11 .
5. Apply MCLK at the appropriate frequency, as discussed in Section 4.6 . SCLK may be applied or set to
master at any time; LRCK may only be applied or set to master while the PDN bit is set to 1.
6. Set the PDN bit to 0.
7. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to
prevent power glitch related issues.
4.10 Recommended Power-Down Sequence
To minimize audible pops when turning off or placing the CODEC in standby:
1. Mute the DACs, PWM outputs and ADCs.
2. Disable soft ramp and zero cross volume transitions.
3. Set the PDN bit to 1.
4. Wait at least 100 µs.
The CODEC will be fully powered down after this 100 µs delay. Prior to the removal of the master clock
(MCLK), this delay of at least 100 µs must be implemented after step
3 to avoid premature disruption
of the CODEC’s power down sequence.
A disruption in the CODEC’s power down sequence (i.e. removing the MCLK signal before this 100 µs
delay) has consequences on both the headphone and speaker amplifiers: The charge pump may stop
abruptly, causing the headphone amplifiers to drive the outputs up to the +VHP supply. Also, the last
state of each ‘+’ and ‘-’ PWM output terminal before the premature removal of MCLK could randomly
be held at either VP or AGND. When this event occurs, it is possible for each PWM terminal to output
opposing potentials, creating a DC source into the speaker voice coil.
The disruption of the CODEC’s power down sequence may also cause clicks and pops on the output
of the DACs as the modulator holds the last output level before the MCLK signal was removed.
5. Optionally, MCLK may be removed at this time.
6. To achieve the lowest operating quiescent current, bring RESET low. All control port registers will be
reset to their default state.
7. Power Supply Removal (Option 1): Switch power supplies to a high impedance state.
8. Power Supply Removal (Option 2): To minimize pops when the power supplies are pulled to ground, a
discharge resistor must be added in parallel with the capacitor on the FILT+ pin. With a 1 M
 resistor
and a 2.2 µF capacitor on FILT+, FILT+ will ramp to ground in approximately 5 seconds. A 1 M
 resistor
on FILT+ reduces the full scale input/output voltage by approximately 0.25 dB.
After step 5 , wait the required time for FILT+ to ramp to ground before pulling VA to ground.
4.11 Required Initialization Settings
The current and thresholds required for various sections in the CODEC must be adjusted by implementing
the initialization settings shown below after power-up sequence step
3 . All performance and power con-
sumption measurements were taken with the following settings: