Cirrus Logic CS42L52 - Manual (Page 36)

36 DS680F2
CS42L52
3/1/13
When configuring the 16-bit SDOUT word length with an 8 kHz sample rate in master mode and when
SCLK is set equal to MCLK, perform the following write sequences:
Register commands ONLY when entering DSP 16-bit, 8 kHz Fs, SCLK=MCLK, master mode:
Register commands when exiting DSP 16-bit, 8 kHz Fs, SCLK=MCLK, master mode:
4.8 Initialization
The CODEC enters a Power-down state on initial power-up. The interpolation and decimation filters, delta-
sigma and PWM modulators, and control port registers are reset. The internal voltage reference, and
switched-capacitor low-pass filters are powered down.
The device remains in Power-down state until the RESET pin is brought high. The control port is accessible
once RESET is high and the desired register settings can be loaded per the descriptions in the
Section 6 .
Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage reference, FILT+, will begin power-
ing up to normal operation. The charge pump slowly powers up and charges the capacitors. Power is then
applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a mut-
ed state. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the MC-
LK/LRCK frequency ratio and normal operation begins.
Register[Bits] Value Description
1 0x0C[1:0] 0x03 Mute the ADC outputs to ensure no audible artifacts are transmitted when changing modes.
2 Refer to Section 4.10 Follow the recommended power down sequence for the HP and PWM outputs.
3 0x02[0] 0x01 Power down the CODEC.
4 0x05[7:0] 0x72 Enable 8 kHz Fs for MCLK=12.000 MHz.
5 0x06[7:0] 0x93 Enable DSP 16-bit master mode.
6 0x07[6] 0x01 Enable SCLK=MCLK.
7 0x33[6] 0x01 Undisclosed register command for enabling mode mentioned above.
8 Refer to Section 4.9 Follow the recommended power up sequence for the HP and PWM outputs.
9 0x02[0] 0x00 Power up the CODEC.
10 0x0C[1:0] 0x00 Unmute the ADC outputs.
Register[Bits] Value Description
1 0x0C[1:0] 0x03 Mute the ADC outputs to ensure no audible artifacts are transmitted when changing modes.
2 Refer to Section 4.10 Follow the recommended power down sequence for the HP and PWM outputs.
3 0x02[0] 0x01 Power down the CODEC.
4 0x05[7:0] 0x20 Enable 48 kHz Fs for MCLK = 12.2880 MHz or re-establish original settings.
5 0x06[7:0] 0x00 Enable Left-Justified 24-bit slave mode or re-establish original settings.
6 0x07[6] 0x00 Disable SCLK=MCLK or re-establish original settings.
7 0x33[6] 0x00 Undisclosed register command for disabling mode mentioned above.
8 Refer to Section 4.9 Follow the recommended power up sequence for the HP and PWM outputs.
9 0x02[0] 0x00 Power up the CODEC.
10 0x0C[1:0] 0x00 Unmute the ADC outputs.
LRCK
SCLK
M S B L S B SDIN
HP/LINE OUTB
L S B L e ft C h a n n e l R ig h t C h a n n e l M S B L S B M S B
Audio Word Length (AWL)
1/fs
HP/LINE OUTA
Figure 19. DSP Mode Format)