Document Outline

• 1. Pin Descriptions
  • 1.1 I/O Pin Characteristics
• 2. Typical Connection Diagram
  • Figure 1. Typical Connection Diagram
• 3. Characteristic and Specification Tables
  • Recommended Operating Conditions
  • Absolute Maximum Ratings
  • Analog Input Characteristics
    • Figure 2. CMRR Test Configuration
  • ADC Digital Filter Characteristics
  • HP Output Characteristics
  • Line Output Characteristics
    • Figure 3. HP Output Test Configuration
    • Figure 4. Line Output Test Configuration
  • Analog Passthrough Characteristics
  • Combined DAC Interpolation & On-Chip Analog FIlter Response
  • Switching Specifications - Serial Port
    • Figure 5. Serial Port Timing (Slave Mode)
    • Figure 6. Serial Port Timing (Master Mode)
  • Switching Specifications - Control Port
    • Figure 7. I·C Control Port Timing
  • Power Supply Rejection (PSRR) Characteristics
  • Digital Interface Specifications & Characteristics
    • Figure 8. Power Consumption Test Configuration
  • Power Consumption - All Supplies = 1.8 V
  • Power Consumption - All Supplies = 2.5 V
• 4. Applications
  • 4.1 Overview
    • 4.1.1 Basic Architecture
    • 4.1.2 Line Inputs
    • 4.1.3 Line and Headphone Outputs (Class H, Ground-Centered Amplifiers)
    • 4.1.4 Fixed-Function DSP Engine
    • 4.1.5 Beep Generator
    • 4.1.6 Power Management
  • 4.2 Analog Inputs
    • Figure 9. Analog Input Signal Flow
    • 4.2.1 Pseudo-Differential Inputs
      • Figure 10. Stereo Pseudo-Differential Input
    • 4.2.2 Automatic Level Control (ALC)
      • Figure 11. ALC Operation
  • 4.3 Analog In to Analog Out Passthrough
  • 4.4 Analog Outputs
    • Figure 12. DSP Engine Signal Flow
    • Figure 13. Analog Output Stage
  • 4.5 Class H Amplifier
    • 4.5.1 Power Control Options
      • Figure 14. Adaptive Mode 00
    • 4.5.2 Power Supply Transitions
      • Figure 15. VHPFILT Transitions
      • Figure 16. VHPFILT Hysteresis
    • 4.5.3 Efficiency
      • Figure 17. Class H Power to Load vs. Power from VCP Supply
  • 4.6 Beep Generator
    • Figure 18. Beep Configuration Options
  • 4.7 Limiter
    • Figure 19. Peak Detect & Limiter
  • 4.8 Serial Port Clocking
  • 4.9 Digital Interface Format
    • Figure 20. I·S Format
  • 4.10 Initialization
  • 4.11 Recommended DAC to HP or Line Power-Up Sequence (Playback)
    • 4.11.1 Recommended Power-Down Sequence
  • 4.12 Recommended PGA to HP or Line Power-Up Sequence (Analog Passthrough)
    • 4.12.1 Recommended Power-Down Sequence
  • 4.13 Required Initialization Settings
  • 4.14 Control Port Operation
    • 4.14.1 I·C Control
      • Figure 21. Control Port Timing, I·C Write
      • Figure 22. Control Port Timing, I·C Read
    • 4.14.2 Memory Address Pointer (MAP)
• 5. Register Quick Reference
• 6. Register Description
  • 6.1 Fab I.D. and Revision Register (Address 01h) (Read Only)
    • 6.1.1 Chip Revision (Read Only)
  • 6.2 Power Control 1 (Address 02h)
    • 6.2.1 Power Down ADC Charge Pump
    • 6.2.2 Power Down ADC x
    • 6.2.3 Power Down
  • 6.3 Power Control 2 (Address 03h)
    • 6.3.1 Headphone Power Control
    • 6.3.2 Line Power Control
  • 6.4 Clocking Control 1 (Address 04h)
    • 6.4.1 Master/Slave Mode
    • 6.4.2 SCLK Polarity
    • 6.4.3 SCLK Equals MCLK
    • 6.4.4 MCLK Divide By 2
    • 6.4.5 MCLK Disable
  • 6.5 Clocking Control 2 (Address 05h)
    • 6.5.1 Speed Mode
    • 6.5.2 32kHz Sample Rate Group
    • 6.5.3 Internal MCLK/LRCK Ratio
  • 6.6 Class H Power Control (Address 06h)
    • 6.6.1 Adaptive Power Adjustment
  • 6.7 Miscellaneous Control (Address 07h)
    • 6.7.1 Digital MUX
    • 6.7.2 Analog Zero Cross
    • 6.7.3 Digital Soft Ramp
    • 6.7.4 Freeze Registers
  • 6.8 ADC, Line, HP MUX (Address 08h)
    • 6.8.1 ADC x Input Select
    • 6.8.2 Line Input Select
    • 6.8.3 Headphone Input Select
  • 6.9 HPF Control (Address 09h)
    • 6.9.1 ADCx High-Pass Filter
    • 6.9.2 ADCx High-Pass Filter Freeze
    • 6.9.3 HPF x Corner Frequency
  • 6.10 Misc. ADC Control (Address 0Ah)
    • 6.10.1 ADC Channel B=A
    • 6.10.2 PGA Channel B=A
    • 6.10.3 Digital Sum
    • 6.10.4 Invert ADC Signal Polarity
    • 6.10.5 ADC Mute
  • 6.11 PGA x MUX, Volume: PGA A (Address 0Bh) & PGA B (Address 0Ch)
    • 6.11.1 Boostx
    • 6.11.2 PGA x Input Select
    • 6.11.3 PGAx Volume
  • 6.12 ADCx Attenuator Control: ADCAATT (Address 0Dh) & ADCBATT (Address 0Eh)
    • 6.12.1 ADCx Volume
  • 6.13 Playback Control 1 (Address 0Fh)
    • 6.13.1 Power Down DSP
    • 6.13.2 HP/Line De-Emphasis
    • 6.13.3 Playback Channels B=A
    • 6.13.4 Invert PCM Signal Polarity
    • 6.13.5 Master Playback Mute
  • 6.14 ADCx Mixer Volume: ADCA (Address 10h) & ADCB (Address 11h)
    • 6.14.1 ADC Mixer Channel x Mute
    • 6.14.2 ADC Mixer Channel x Volume
  • 6.15 PCMx Mixer Volume: PCMA (Address 12h) & PCMB (Address 13h)
    • 6.15.1 PCM Mixer Channel x Mute
    • 6.15.2 PCM Mixer Channel x Volume
  • 6.16 Beep Frequency & On Time (Address 14h)
    • 6.16.1 Beep Frequency
    • 6.16.2 Beep On Time
  • 6.17 Beep Volume & Off Time (Address 15h)
    • 6.17.1 Beep Off Time
    • 6.17.2 Beep Volume
  • 6.18 Beep & Tone Configuration (Address 16h)
    • 6.18.1 Beep Configuration
    • 6.18.2 Treble Corner Frequency
    • 6.18.3 Bass Corner Frequency
    • 6.18.4 Tone Control Enable
  • 6.19 Tone Control (Address 17h)
    • 6.19.1 Treble Gain
    • 6.19.2 Bass Gain
  • 6.20 Master Volume Control: MSTA (Address 18h) & MSTB (Address 19h)
    • 6.20.1 Master Volume Control
  • 6.21 Headphone Volume Control: HPA (Address 1Ah) & HPB (Address 1Bh)
    • 6.21.1 Headphone Channel x Mute
    • 6.21.2 Headphone Volume Control
  • 6.22 Line Volume Control: LINEA (Address 1Ch) & LINEB (Address 1Dh)
    • 6.22.1 Line Channel x Mute
    • 6.22.2 Line Volume Control
  • 6.23 Analog Input Advisory Volume (Address 1Eh)
    • 6.23.1 Analog Input Advisory Volume
  • 6.24 Digital Input Advisory Volume (Address 1Fh)
    • 6.24.1 Digital Input Advisory Volume
  • 6.25 ADC & PCM Channel Mixer (Address 20h)
    • 6.25.1 PCM Mix Channel Swap
    • 6.25.2 ADC Mix Channel Swap
  • 6.26 Limiter Min/Max Thresholds (Address 21h)
    • 6.26.1 Limiter Maximum Threshold
    • 6.26.2 Limiter Cushion Threshold
  • 6.27 Limiter Control, Release Rate (Address 22h)
    • 6.27.1 Peak Detect and Limiter
    • 6.27.2 Peak Signal Limit All Channels
    • 6.27.3 Limiter Release Rate
  • 6.28 Limiter Attack Rate (Address 23h)
    • 6.28.1 Limiter Attack Rate
  • 6.29 ALC Enable & Attack Rate (Address 24h)
    • 6.29.1 ALCx
    • 6.29.2 ALC Attack Rate
  • 6.30 ALC Release Rate (Address 25h)
    • 6.30.1 ALC Release Rate
  • 6.31 ALC Threshold (Address 26h)
    • 6.31.1 ALC Maximum Threshold
    • 6.31.2 ALC Minimum Threshold
  • 6.32 Noise Gate Control (Address 27h)
    • 6.32.1 Noise Gate All Channels
    • 6.32.2 Noise Gate Enable
    • 6.32.3 Noise Gate Threshold and Boost
    • 6.32.4 Noise Gate Delay Timing
  • 6.33 ALC and Limiter Soft Ramp, Zero Cross Disables (Address 28h)
    • 6.33.1 ALCx Soft Ramp Disable
    • 6.33.2 ALCx Zero Cross Disable
    • 6.33.3 Limiter Soft Ramp Disable
  • 6.34 Status (Address 29h) (Read Only)
    • 6.34.1 HPDETECT Pin Status (Read Only)
    • 6.34.2 Serial Port Clock Error (Read Only)
    • 6.34.3 DSP Engine Overflow (Read Only)
    • 6.34.4 MIXx Overflow (Read Only)
    • 6.34.5 ADCx Overflow (Read Only)
  • 6.35 Charge Pump Frequency (Address 2Ah)
    • 6.35.1 Charge Pump Frequency
• 7. PCB Layout Considerations
  • 7.1 Power Supply
  • 7.2 Grounding
  • 7.3 QFN Thermal Pad
• 8. Analog Volume Non-Linearity (DNL & INL)
  • Figure 23. PGA Step Size vs. Volume Setting
  • Figure 24. PGA Output Volume vs. Volume Setting
  • Figure 25. HP/Line Step Size vs. Volume Setting
  • Figure 26. HP/Line Output Volume vs. Volume Setting
• 9. ADC & DAC Digital Filters
  • Figure 27. ADC Passband Ripple
  • Figure 28. ADC Stopband Rejection
  • Figure 29. ADC Transition Band
  • Figure 30. ADC Transition Band Detail
  • Figure 31. DAC Passband Ripple
  • Figure 32. DAC Stopband
  • Figure 33. DAC Transition Band
  • Figure 34. DAC Transition Band (Detail)
• 10. Parameter Definitions
• 11. Package Dimensions
  • Thermal Characteristics
• 12. Ordering Information
• 13. References
• 14. Revision History