Cirrus Logic CS4392 - Manual (Page 34)

CS4392
34 DS459PP3
SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE
(Inputs: logic 0 = AGND, logic 1 = VL)
Notes: 6. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Parameter Symbol Min Max Unit
I
2
C Mode
SCL Clock Frequency
f
scl
- 100 kHz
RST Rising Edge to Start t
irs
500 - ns
Bus Free Time Between Transmissions t
buf
4.7 - µs
Start Condition Hold Time (prior to first clock pulse) t
hdst
4.0 - µs
Clock Low time t
low
4.7 - µs
Clock High Time t
high
4.0 - µs
Setup Time for Repeated Start Condition t
sust
4.7 - µs
SDA Hold Time from SCL Falling (Note 6) t
hdd
0 - µs
SDA Setup time to SCL Rising t
sud
250 - ns
Rise Time of Both SDA and SCL Lines t
r
- 1 µs
Fall Time of Both SDA and SCL Lines t
f
- 300 ns
Setup Time for Stop Condition t
susp
4.7 - µs
t
buf t
hdst
t
hdst
t
lo w
t r
t f
t
hdd
t
high
t sud t sust
t susp
Stop S ta rt S ta rt Stop
R e p e a te d
S D A
S C L
t
irs
R S T
Figure 38. I 2 C Mode Control Port Timing