Cirrus Logic CDB43L21 - Manual (Page 11)

DS723DB1 11
CDB43L21
3. HARDWARE MODE CONTROL
The CDB may be configured without the use of a software control port through the use of two switches, “FPGA H/W
Control” and “CS43L21 H/W Control.” These switches are enabled in Hardware Mode only and ignored in Software
Mode. The CDB43L21 automatically enters Hardware Mode upon initial power up, when exiting Software Mode,
upon termination of the Cirrus FlexGUI software, or by disconnecting the RS-232 serial cable.
3.1 FPGA H/W Control
The “FPGA H/W Control” switch sets up the CDB in 11 pre-defined routing topologies in Hardware Mode.
The tables and figures below describe each switch setting. The At-A-Glance Controls table provides a quick
reference for all presets.
3.2 CS43L21 H/W Control
The stand-alone “CS43L21 H/W Control” switch controls the Hardware Mode options of the CS43L21. A
description of each switch is outlined in the following table:
At-A-Glance Controls
S[3:2] S[1] S[0]
00 - CS8415 MCLK / CS8415 clocks/data route through FPGA
0 - CS43L21 Slave Routing
1 - CS43L21 Master Routing
0 - Normal Operation
1 - Reserved
01 - I/O Header MCLK / I/O Header clocks/data route through FPGA
10 - Oscillator MCLK / I/O Header clocks/data route through FPGA
11 - Reserved
Signal
Routing
S[3:0] General Description Detailed Description
CS8415 MCLK
1
Figure 4
0000 CS8415 Clocks/Data 1) CS8415 masters MCLK. 2) CS8415 masters PCM clocks.
3) CS8415 data into SDIN.
I/O MCLK
2
Figure 5
0100 I/O Clocks/Data 1) I/O masters MCLK. 2) I/O masters PCM clocks.
3) I/O data into SDIN.
3
Figure 6
0110 CS43L21 Clocks, I/O Data 1) I/O masters MCLK. 2) CS43L21 masters PCM clocks.
3) I/O data into SDIN.
Oscillator MCLK
4
Figure 7
1000 I/O Clocks/Data 1) Oscillator masters MCLK. 2) I/O masters PCM clocks.
3) I/O data into SDIN.
5
Figure 8
1010 CS43L21 Clocks, I/O Data 1) Oscillator masters MCLK. 2) CS43L21 masters PCM
clocks.
3) I/O data into SDIN.
Table 1. MCLK and Clock/Data Routing Options
Switch Position Function
M/S
LO LRCK and SCLK are inputs to CS43L21
HI LRCK and SCLK are outputs to CS43L21
MCLKDIV2
LO Internal MCLK to CS43L21 not divided
HI Internal MCLK to CS43L21 divided by 2
I2S/LJ
LO CS43L21 Interface Format: Left-Justified
HI CS43L21 Interface Format: I²S
DE-EMPHASIS
LO No internal De-emphasis applied to CS43L21
HI 44.1 kHz internal De-emphasis applied to CS43L21
Table 2. CS43L21 H/W Mode Control