1 general configuration tab, Figure 1. general configuration tab, Figure 1.general configuration tab – Cirrus Logic CDB43L21 User Manual
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DS723DB1
CDB43L21
2.1
General Configuration Tab
The “General Configuration” tab provides high-level control of signal routing on the CDB43L21. This tab also
includes basic controls for the CS43L21 for quickly setting up the CDB43L21 in simple configurations. Sta-
tus text detailing the CS43L21’s specific configuration is shown in parenthesis or appears directly below the
associated control. This text may change depending on the setting of the associated control. A description
of each control group is outlined below:
CS43L21 Basic Configuration - Includes basic register controls in the CS43L21 used for setting up power
status, interface format and clocking functions. See
for more controls in the
CS43L21.
S/PDIF Receiver Control - Includes all available Hardware Mode controls for setting up the CS8415.
Clock/Data Routing and CS43L21 Reset - Includes controls used for routing clocks and data between the
CS43L21, CS8415, oscillator and the I/O stake header. Also includes a reset control for the CS43L21.
Update - Reads all registers in the FPGA and CS43L21 and reflects the current values in the GUI.
Reset - Resets FPGA to default routing configuration.
Figure 1. General Configuration Tab