Cirrus Logic CDB43L21 - Manual (Page 5)

DS723DB1 5
CDB43L21
Section 2. “Software Mode Control” on page 7 and Section 3. “Hardware Mode Control” on page 11 provide
configuration details.
1.5 CS8415 Digital Audio Receiver
A complete description of the CS8415 receiver ( Figure 12 on page 18 ) and a discussion of the digital audio
interface are included in the CS8415 data sheet.
The CS8415 converts the input S/PDIF data stream from either the optical or the RCA connector into PCM
data for the CS43L21. The CS8415 operates in master or slave mode, generates a 256xFs master clock,
and can operate in either the Left-Justified or I²S interface format.
Selections are made in the control port of the FPGA, accessible through the “General Configurations” tab
of the Cirrus FlexGUI software or through the on-board “FPGA H/W Control” switches.
Section 2. “Software
Mode Control” on page 7 and Section 3. “Hardware Mode Control” on page 11 provide configuration details.
1.6 Oscillator
The on-board oscillator provides one of the system master clocks. Selections are made in the control port
of the FPGA, accessible through the “General Configurations” tab of the Cirrus FlexGUI software or through
the on-board switches, “FPGA H/W Control.”
Section 2. “Software Mode Control” on page 7 and Section 3.
“Hardware Mode Control” on page 11 provide configuration details.
The oscillator is mounted in pin sockets, allowing easy removal or replacement. Additional sockets are also
installed, allowing the optional use of a half-can- or full-can-sized oscillator.
1.7 I/O Stake Headers
The evaluation board has been designed to allow interfacing with external systems via a serial port header
(reference designation J5) and a control port header, “CS43L21 S/W Control.” The serial port header pro-
vides access to the serial audio signals required to interface with a DSP (
Figure 13 on page 19 ). Selections
are made in the control port of the FPGA, accessible through the “General Configurations” tab of the Cirrus
FlexGUI software or through the on-board “FPGA H/W Control” switches.
Section 2. “Software Mode Con-
trol” on page 7 and Section 3. “Hardware Mode Control” on page 11 provide configuration details.
The control port header provides bidirectional access to the SPI™/I²C ® control port signals by simply remov-
ing all the shunt jumpers from the “PC” position. The user may then choose to connect a ribbon cable to the
“CONTROL” position, allowing operation of the CS43L21 in a user-application for system development. A
single “GND” row for the ribbon cable’s ground connection is provided to maintain signal integrity. Two un-
populated pull-up resistors are also available should the user choose to use the CDB for the I²C power rail.
1.8 Analog Outputs
RCA connectors are connected directly to the output of the CS43L21 to allow evaluation of the ground-cen-
tered analog outputs. The Right Channel and Left Channel stake headers optionally connect a passive-fil-
tered output to the RCA connectors. For evaluation of the CS43L21’s drive strength into a load, the 16 W
HP Load stake headers connect the analog outputs to 16 W. Headphones may also be connected to the
1/8th inch jack. When connecting headphones, the 16
Ω load resistors should be disconnected by removing
the jumpers on each stake header.
One of the analog outputs may be connected to a speaker driver through the “Speaker” stake header. A
mono speaker may then be driven via the red and black banana jack. The red banana jack designates the
positive terminal and the black designates the negative.