Document Outline

• Features & Description
• 1. Overview
• 2. Pin Descriptions
  • Digital Pins and Serial Data I/O
  • Analog Inputs / Outputs
  • Power Supply Connections
  • Clock Generator
  • Thermal Pad
  • 2.1 Analog Pins
    • 2.1.1 Voltage Inputs
    • 2.1.2 Current Inputs
    • 2.1.3 Voltage Reference
    • 2.1.4 Crystal Oscillator
  • 2.2 Digital Pins
    • 2.2.1 Reset Input
    • 2.2.2 CPU Clock Output
    • 2.2.3 Digital Outputs
    • 2.2.4 UART/SPI™ Serial Interface
    • 2.2.5 SPI
    • 2.2.6 UART
    • 2.2.7 MODE Pin
• 3. Characteristics and Specifications
  • Recommended Operating Conditions
  • Power Measurement Characteristics
  • Typical Load Performance
  • Analog Characteristics
    • Analog Inputs (Current Channels)
    • Analog Inputs (Voltage Channels)
    • Temperature
    • Power Supplies
  • Voltage Reference
  • Digital Characteristics
    • Master Clock Characteristics
    • Filter Characteristics
    • Input/Output Characteristics
  • Switching Characteristics
    • Start-up
    • SPI Timing
    • UART Timing
  • Absolute Maximum Ratings
• 4. Signal Flow Description
  • 4.1 Analog-to-Digital Converters
  • 4.2 Decimation Filters
  • 4.3 IIR Filters
  • 4.4 Phase Compensation
  • 4.5 DC Offset and Gain Correction
  • 4.6 High-pass and Phase Matching Filters
  • 4.7 Digital Integrators
  • 4.8 Low-rate Calculations
    • 4.8.1 Fixed Number of Samples Averaging
    • 4.8.2 Line-cycle Synchronized Averaging
    • 4.8.3 RMS Current and Voltage
    • 4.8.4 Active Power
    • 4.8.5 Reactive Power
    • 4.8.6 Apparent Power
    • 4.8.7 Peak Voltage and Current
    • 4.8.8 Power Factor
  • 4.9 Average Active Power Offset
  • 4.10 Average Reactive Power Offset
• 5. Functional Description
  • 5.1 Power-on Reset
  • 5.2 Power Saving Modes
  • 5.3 Zero-crossing Detection
  • 5.4 Line Frequency Measurement
  • 5.5 Energy Pulse Generation
    • 5.5.1 Pulse Rate
    • 5.5.2 Pulse Width
  • 5.6 Voltage Sag, Voltage Swell, and Overcurrent Detection
  • 5.7 Phase Sequence Detection
  • 5.8 Temperature Measurement
  • 5.9 Anti-creep
  • 5.10 Register Protection
    • 5.10.1 Write Protection
    • 5.10.2 Register Checksum
• 6. Host Commands and Registers
  • 6.1 Host Commands
    • 6.1.1 Memory Access Commands
      • 6.1.1.1 Page Select
      • 6.1.1.2 Register Read
      • 6.1.1.3 Register Write
    • 6.1.2 Instructions
    • 6.1.3 Checksum
    • 6.1.4 Serial Time Out
  • 6.2 Hardware Registers Summary (Page 0)
  • 6.3 Software Registers Summary (Page 16)
  • 6.4 Software Registers Summary (Page 17)
  • 6.5 Software Registers Summary (Page 18)
  • 6.6 Register Descriptions
    • 6.6.1 Configuration 0 (Config0) – Page 0, Address 0
    • 6.6.2 Configuration 1 (Config1) – Page 0, Address 1
    • 6.6.3 Configuration 2 (Config2) – Page 16, Address 0
    • 6.6.4 Phase Compensation (PC) – Page 0, Address 5
    • 6.6.5 UART Control (SerialCtrl) – Page 0, Address 7
    • 6.6.6 Pulse Output Width (PulseWidth) – Page 0, Address 8
    • 6.6.7 Pulse Output Rate (PulseRate) – Page 18, Address 28
    • 6.6.8 Pulse Output Control (PulseCtrl) – Page 0, Address 9
    • 6.6.9 Register Lock Control (RegLock) – Page 0, Address 34
    • 6.6.10 Phase Sequence Detection and Control (PSDC) – Page 0, Address 48
    • 6.6.11 Checksum of Critical Registers (RegChk) – Page 16, Address 1
    • 6.6.12 Interrupt Status (Status0) – Page 0, Address 23
    • 6.6.13 Interrupt Mask (Mask) – Page 0, Address 3
    • 6.6.14 Chip Status 1 (Status1) – Page 0, Address 24
    • 6.6.15 Chip Status 2 (Status2) – Page 0, Address 25
    • 6.6.16 Line to Sample Frequency Ratio (Epsilon) – Page 16, Address 49
    • 6.6.17 No-Load Threshold (LoadMIN ) – Page 16, Address 58
    • 6.6.18 Sample Count (SampleCount) – Page 16, Address 51
    • 6.6.19 Cycle Count (CycleCount) – Page 18, Address 62
    • 6.6.20 Filter Settling Time for Conversion Startup (TSETTLE) – Page 16, Address 57
    • 6.6.21 System Gain (SysGAIN ) – Page 16, Address 60
    • 6.6.22 Rogowski Coil Integrator Gain (IntGAIN ) – Page 18, Address 43
    • 6.6.23 System Time (Time) – Page 16, Address 61
    • 6.6.24 Voltage 1 Sag Duration (V1SagDUR ) – Page 17, Address 0
    • 6.6.25 Voltage 1 Sag Level (V1SagLEVEL ) – Page 17, Address 1
    • 6.6.26 Current 1 Overcurrent Duration ( I1OverDUR ) – Page 17, Address 4
    • 6.6.27 Current 1 Overcurrent Level ( I1OverLEVEL ) – Page 17, Address 5
    • 6.6.28 Voltage 2 Sag Duration (V2SagDUR ) – Page 17, Address 8
    • 6.6.29 Voltage 2 Sag Level (V2SagLEVEL ) – Page 17, Address 9
    • 6.6.30 Current 2 Overcurrent Duration (I 2OverDUR ) – Page 17, Address 12
    • 6.6.31 Current 2 Overcurrent Level (I 2OverLEVEL ) – Page 17, Address 13
    • 6.6.32 Voltage 1 Swell Duration (V1SwellDUR ) – Page 18, Address 46
    • 6.6.33 Voltage 1 Swell Level (V1SwellLEVEL ) – Page 18, Address 47
    • 6.6.34 Voltage 2 Swell Duration (V2SwellDUR ) – Page 18, Address 50
    • 6.6.35 Voltage 2 Swell Level (V 2SwellLEVEL ) – Page 18, Address 51
    • 6.6.36 Instantaneous Current 1 (I1) – Page 16, Address 2
    • 6.6.37 Instantaneous Voltage 1 (V1) – Page 16, Address 3
    • 6.6.38 Instantaneous Active Power 1 (P1) – Page 16, Address 4
    • 6.6.39 Active Power 1 (P1AVG ) – Page 16, Address 5
    • 6.6.40 RMS Current 1 ( I1RMS ) – Page 16, Address 6
    • 6.6.41 RMS Voltage 1 (V1RMS ) – Page 16, Address 7
    • 6.6.42 Instantaneous Current 2 (I2) – Page 16, Address 8
    • 6.6.43 Instantaneous Voltage 2 (V2) – Page 16, Address 9
    • 6.6.44 Instantaneous Active Power 2 (P2) – Page 16, Address 10
    • 6.6.45 Active Power 2 (P2AVG ) – Page 16, Address 11
    • 6.6.46 RMS Current 2 (I 2RMS) – Page 16, Address 12
    • 6.6.47 RMS Voltage 2 (V2RMS ) – Page 16, Address 13
    • 6.6.48 Reactive Power 1 (Q1Avg ) – Page 16, Address 14
    • 6.6.49 Instantaneous Quadrature Power 1 (Q1) – Page 16, Address 15
    • 6.6.50 Reactive Power 2 (Q2Avg ) – Page 16, Address 16
    • 6.6.51 Instantaneous Quadrature Power 2 (Q2) – Page 16, Address 17
    • 6.6.52 Peak Current 1 (I1PEAK) – Page 0, Address 37
    • 6.6.53 Peak Voltage 1 (V1PEAK) – Page 0, Address 36
    • 6.6.54 Apparent Power 1 (S1) – Page 16, Address 20
    • 6.6.55 Power Factor 1 (PF1) – Page 16, Address 21
    • 6.6.56 Peak Current 2 (I2PEAK) – Page 0, Address 39
    • 6.6.57 Peak Voltage 2 (V2PEAK) – Page 0, Address 38
    • 6.6.58 Apparent Power 2 (S2) – Page 16, Address 24
    • 6.6.59 Power Factor 2 (PF2) – Page 16, Address 25
    • 6.6.60 Temperature (T) – Page 16, Address 27
    • 6.6.61 Total Active Power (PSUM ) – Page 16, Address 29
    • 6.6.62 Total Apparent Power (SSUM ) – Page 16, Address 30
    • 6.6.63 Total Reactive Power (QSUM ) – Page 16, Address 31
    • 6.6.64 DC Offset for Current (I1DCOFF , I2DCOFF ) – Page 16, Address 32, 39
    • 6.6.65 DC Offset for Voltage (V1DCOFF , V2DCOFF ) – Page 16, Address 34, 41
    • 6.6.66 Gain for Current (I1GAIN , I2GAIN ) – Page 16, Address 33, 40
    • 6.6.67 Gain for Voltage (V1GAIN , V2GAIN ) – Page 16, Address 35, 42
    • 6.6.68 Average Active Power Offset (P1OFF, P2OFF ) – Page 16, Address 36, 43
    • 6.6.69 Average Reactive Offset (Q1OFF , Q2OFF ) – Page 16, Address 38, 45
    • 6.6.70 AC Offset for Current (I1ACOFF, I 2ACOFF ) – Page 16, Address 37, 44
    • 6.6.71 Temperature Gain (TGAIN ) – Page 16, Address 54
    • 6.6.72 Temperature Offset (TOFF ) – Page 16, Address 55
    • 6.6.73 Calibration Scale (Scale) – Page18, Address 63
    • 6.6.74 V-Channel Zero-crossing Threshold (VZXLEVEL) – Page 18, Address 58
    • 6.6.75 I-Channel Zero-crossing Threshold (IZXLEVEL) – Page 18, Address 24
    • 6.6.76 Zero-crossing Number (ZXNUM) – Page 0, Address 55
• 7. System Calibration
  • 7.1 Calibration in General
    • 7.1.1 Offset Calibration
      • 7.1.1.1 DC Offset Calibration
      • 7.1.1.2 AC Offset Calibration
    • 7.1.2 Gain Calibration
    • 7.1.3 Calibration Order
  • 7.2 Phase Compensation
  • 7.3 Temperature Sensor Calibration
    • 7.3.1 Temperature Offset and Gain Calibration
• 8. Basic Application Circuits
• 9. Package Dimensions
• 10. Ordering Information
• 11. Environmental, Manufacturing, and Handling Information
• 12. Revision History