Rockwell Automation MPP Processor Moduile - Manual (Page 13)

MPP October 2005 – Issue 6 13
Triguard SC300E MPP Processor Module
configured I/O slots to determine their status. All I/O modules have identity type registers
which allow the hot repair task to confirm the status of all fitted modules.
Circuit details
The block diagram (Figure 2-3 ) shows the main functional areas of the MPP circuit. Overall
control of the circuit is by the microprocessor. At a lower level, individual parts of the circuit are
controlled by Programmable logic (PALs) and peripheral devices.
Power supplies
The two 5.4Vdc supplies from the chassis PSUs are fused on entry to the MPP by 3A fuses
F1 and F2 respectively. Both supplies are then fed via three pairs of auctioneering diodes to
three 5V regulators. Each of the regulator outputs feeds a separate area of the MPP circuit.
The 12V outputs from the chassis PSUs are not used by the MPP.
System clock and supervisory circuits
The 32MHz system clock to the microprocessor is derived from a crystal oscillator. 16MHz
and 8MHz clock signals for use elsewhere in the system are obtained by dividing the system
clock. A microprocessor supervisory chip operates as follows:
• Generates a reset signal to the microprocessor during a cold start
• Monitors the charge state of the backup batteries and drives the Battery LED on the
front panel
• Generates the basic watchdog signal. This signal controls the Run LED on the front
panel. A secondary watchdog circuit monitors the Address Strobe pulses from the
microprocessor. Its output controls the Health LED on the front panel.
Memory
The MPP has eight 32-pin DIL sockets used to mount the EPROMs which contain the
operating system RTTS.
Ten 32-pin sockets are provided for byte-wide SRAM in two banks of five. SRAM is supported by
one or two backup batteries in the absence of an external power supply.
Error detection and correction (EDC)
A 32-bit EDC processor detects and corrects single bit errors during reads from SRAM.
Dual port controller
The dual port controller controls accesses to SRAM by the Microprocessor and the
Communicator.