Pci bus test, Cpu cache loop, Rebuilding redboot – Comtrol eCos User Manual
Page 239: Interrupts
Chapter 5. Installation and Testing
PCI Bus Test
This tests the secondary PCI-X bus and socket. This test requires that an IQ80310 board be plugged into the
secondary slot of the IOP80321 board. The test assumes at least 32MB of installed memory on the IQ80310. That
memory is mapped into the IOP80321 address space and the memory tests are run on that memory.
CPU Cache Loop
This test puts the CPU into a tight loop run entirely from the ICache. This should prevent all external bus accesses.
Rebuilding RedBoot
These shell variables provide the platform-specific information needed for building RedBoot according to the
procedure described in
export TARGET=iq80321
export ARCH_DIR=arm
export PLATFORM_DIR=xscale/iq80321
The names of configuration files are listed above with the description of the associated modes.
Interrupts
RedBoot uses an interrupt vector table which is located at address 0x8004. Entries in this table are pointers to
functions with this protoype::
int irq_handler( unsigned vector, unsigned data )
On
an
IQ80321
board,
the
vector
argument
is
one
of
32
interrupts
defined
in
hal/arm/xscale/verde/current/include/hal_var_ints.h:
:
// *** 80200 CPU ***
#define CYGNUM_HAL_INTERRUPT_DMA0_EOT
0
#define CYGNUM_HAL_INTERRUPT_DMA0_EOC
1
#define CYGNUM_HAL_INTERRUPT_DMA1_EOT
2
#define CYGNUM_HAL_INTERRUPT_DMA1_EOC
3
#define CYGNUM_HAL_INTERRUPT_RSVD_4
4
#define CYGNUM_HAL_INTERRUPT_RSVD_5
5
#define CYGNUM_HAL_INTERRUPT_AA_EOT
6
#define CYGNUM_HAL_INTERRUPT_AA_EOC
7
#define CYGNUM_HAL_INTERRUPT_CORE_PMON
8
#define CYGNUM_HAL_INTERRUPT_TIMER0
9
#define CYGNUM_HAL_INTERRUPT_TIMER1
10
#define CYGNUM_HAL_INTERRUPT_I2C_0
11
#define CYGNUM_HAL_INTERRUPT_I2C_1
12
#define CYGNUM_HAL_INTERRUPT_MESSAGING
13
#define CYGNUM_HAL_INTERRUPT_ATU_BIST
14
#define CYGNUM_HAL_INTERRUPT_PERFMON
15
#define CYGNUM_HAL_INTERRUPT_CORE_PMU
16
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