Comtrol eCos - Manual (Page 342)

Chapter 11. Porting Guide
In architectures such as the MIPS and PowerPC where cache instructions are part of the ISA, most of the actual
cache operations are implemented in the architecture HAL. In this case the variant HAL only needs to define the
cache dimensions. The following are the cache dimensions defined in the MIPS VR4300 variant
var_cache.h .
// Data cache
#define HAL_DCACHE_SIZE (8*1024) // Size of data cache in bytes
#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
#define HAL_DCACHE_WAYS 1 // Associativity of the cache
// Instruction cache
#define HAL_ICACHE_SIZE (16*1024) // Size of cache in bytes
#define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
#define HAL_ICACHE_WAYS 1 // Associativity of the cache
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
Additional cache macros, or overrides for the defaults, may also appear in here. While some architectures have in-
structions for managing cache lines, overall enable/disable operations may be handled via variant specific registers.
If so then
var_cache.h should also define the HAL_XCACHE_ENABLE() and HAL_XCACHE_DISABLE() macros.
If there are any generic features that the variant does not support (cache locking is a typical example) then
var_cache.h may need to disable definitions of certain operations. It is architecture dependent exactly how this
is done.
Architecture HAL Porting
A new architecture HAL is the most complex HAL to write, and it the least easily described. Hence this section is
presently nothing more than a place holder for the future.
HAL Architecture Porting Process
The easiest way to make a new architecture HAL is simply to copy an existing architecture HAL of an, if possible,
closely matching architecture and change all the files to match the new architecture. The MIPS architecture HAL
should be used if possible, as it has the appropriate layout and coding conventions. Other HALs may deviate from
that norm in various ways.
Note: eCos is written for GCC. It requires C and C++ compiler support as well as a few compiler features
introduced during eCos development - so compilers older than eCos may not provide these features. Note
that there is no C++ support for any 8 or 16 bit CPUs. Before you can undertake an eCos port, you need the
required compiler support.
The following gives a rough outline of the steps needed to create a new architecture HAL. The exact order and
set of steps needed will vary greatly from architecture to architecture, so a lot of flexibility is required. And of
course, if the architecture HAL is to be tested, it is necessary to do variant and platform ports for the initial target
simultaneously.
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