Comtrol eCos - Manual (Page 292)

Chapter 9. HAL Interfaces
These definitions are usually found in the header file cyg/hal/hal_cache.h . This file may be defined in the
architecture, variant or platform HAL, depending on where the caches are implemented for the target. Often there
will be a generic implementation of the cache control macros in the architecture HAL with the ability to override
or undefine them in the variant or platform HAL. Even when the implementation of the cache macros is in the
architecture HAL, the cache dimensions will be defined in the variant or platform HAL. As with other files, the
variant or platform specific definitions are usually found in
cyg/hal/var_cache.h and cyg/hal/plf_cache.h
respectively. These files are include automatically by this header, so need not be included explicitly.
There are versions of the macros defined here for both the Data and Instruction caches. these are distinguished by
the use of either
DCACHE or ICACHE in the macro names. Some architectures have a unified cache, where both data
and instruction share the same cache. In these cases the control macros use UCACHE and the DCACHE and ICACHE
macros will just be calls to the UCACHE version. In the following descriptions, XCACHE is used to stand for any of
these. Where there are issues specific to a particular cache, this will be explained in the text.
There might be target specific restrictions on the use of some of the macros which it is the user’s responsibility to
comply with. Such restrictions are documented in the header file with the macro definition.
Note that destructive cache macros should be used with caution. Preceding a cache invalidation with a cache syn-
chronization is not safe in itself since an interrupt may happen after the synchronization but before the invalidation.
This might cause the state of dirty data lines created during the interrupt to be lost.
Depending on the architecture’s capabilities, it may be possible to temporarily disable the cache while doing the
synchronization and invalidation which solves the problem (no new data would be cached during an interrupt).
Otherwise it is necessary to disable interrupts while manipulating the cache which may take a long time.
Some platform HALs now support a pair of cache state query macros: HAL_ICACHE_IS_ENABLED( x ) and
HAL_DCACHE_IS_ENABLED( x ) which set the argument to true if the instruction or data cache is enabled, re-
spectively. Like most cache control macros, these are optional, because the capabilities of different targets and
boards can vary considerably. Code which uses them, if it is to be considered portable, should test for their exis-
tence first by means of
#ifdef . Be sure to include < cyg/hal/hal_cache.h > in order to do this test and (maybe)
use the macros.
Cache Dimensions
HAL_XCACHE_SIZE
HAL_XCACHE_LINE_SIZE
HAL_XCACHE_WAYS
HAL_XCACHE_SETS
These macros define the size and dimensions of the Instruction and Data caches.
HAL_XCACHE_SIZE
Defines the total size of the cache in bytes.
HAL_XCACHE_LINE_SIZE
Defines the cache line size in bytes.
HAL_XCACHE_WAYS
Defines the number of ways in each set and defines its level of associativity. This would be 1 for a direct
mapped cache, 2 for a 2-way cache, 4 for 4-way and so on.
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