Table 11-4. watchdog timeout intervals -14, Table 11-5. watchdog timer-related bits -14, Table 11-4. watchdog timeout intervals – Maxim Integrated Ultra-High-Speed Flash Microcontroller User Manual

Page 134: Table 11-5. watchdog timer-related bits

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11-14

Ultra-High-Speed Flash

Microcontroller User’s Guide

As discussed above, the watchdog timer has several SFR bits that contribute to its operation. It can be enabled to function as either

a reset source, interrupt source, software polled timer, or any combination of the three. Both the reset and the interrupt have status

flags. The watchdog also has a bit that restarts the timer. Table 11-5 shows the watchdog timer-related bits. Detailed bit descriptions

can be found in Section 4.

WATCHDOG TIMEOUT

(IN NUMBER OF OSCILLATOR CLOCKS)

SYSTEM CLOCK MODE

PMR REGISTER BITS

4X/2X, CD1, CD0

WD1:0 = 00b

WD1:0 = 01b

WD1:0 = 10b

WD1:0 = 11b

Crystal multiply mode 4X

100

2

15

2

18

2

21

2

24

Crystal multiply mode 2X

000

2

16

2

19

2

22

2

25

Divide-by-1 (default)

X01, X10

2

17

2

20

2

23

2

26

Power management mode

(divide-by-1024)

X11

2

27

2

30

2

33

2

36

Table 11-4. Watchdog Timeout Intervals

BIT NAMES

DESCRIPTION

REGISTER LOCATION

BIT POSITIONS

EWT

Enable watchdog timer reset

WDCON – D8h

WDCON.1

RWT

Reset watchdog timer

WDCON – D8h

WDCON.0

WD1,WD0

Watchdog interval control bits 1, 0

CKCON – 8Eh

CKCON.7,6

WTRF

Watchdog timer reset flag

WDCON – D8h

WDCON.2

EWDI

Enable watchdog timer interrupt

EIE – E8h

EIE.4

WDIF

Watchdog interrupt flag

WDCON – D8h

WDCON.3

Table 11-5. Watchdog Timer-Related Bits

Maxim Integrated

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