Maxim Integrated Ultra-High-Speed Flash Microcontroller User Manual
Page 62
5-15
Page Mode 2 External Timing—Pages 1:0 = 11b
The page mode 2 external bus structure multiplexes port 2 between address MSB and data. The address LSB is provided exclusive-
ly on port 0. ALE is used to latch the address MSB only when needed, and PSEN serves as the enable for external program memory.
To invoke page mode 2 operation, the PAGES 1:0 bits must be set to 11b, followed by the setting of the PAGEE bit. In the page mode
2 configuration, a page-hit program memory cycle is two system clocks in length, while the page-miss program memory cycle requires
four system clocks. All data memory cycles are four system clocks in length.
Figure 5-21 shows the fetch of the CLR C instruction (1 byte, 1 cycle) during a page-miss memory cycle, followed by the fetch of the RRC
A instruction (1 byte, one cycle) during a page-hit memory cycle. The next instruction, XCH A, @R0 (1 byte, three cycles), requires three
memory cycles to execute, so two stall cycles must be inserted for it to complete prior to the next instruction being read.
Figure 5-22 illustrates the LJMP (3 bytes, three cycles) instruction, whose destination address is on a different 256-byte page than the
LJMP instruction, thus resulting in a page-miss memory cycle.
SYSCLK
ALE
PSEN
PORT2
PORT0
MSB
LSB
LSB
LSB
02
50
00
MISS
HIT
HIT
LSB
MISS
LSB
HIT
LJMP addr16
LSB
HIT
MSB
Figure 5-22. Page Mode 2: (Page Miss) – LJMP Addr16 – (Page Miss)
SYSCLK
ALE
PSEN
PORT2
PORT0
MSB
C3
13
C6
LSB
LSB
LSB
MISS
HIT
HIT
CLR C
RRC A
LSB Address
HIT
LSB
HIT
XCH A, @R0
stall
stall
Figure 5-21. Page Mode 2: (Page Miss) – CLR C – RRC A – XCH A, @R0
Ultra-High-Speed Flash
Microcontroller User’s Guide
Maxim Integrated