Maxim Integrated Ultra-High-Speed Flash Microcontroller - Manual (Page 6)

Ultra-High-Speed Flash
Microcontroller User’s Guide
SECTION 3: ARCHITECTURE
The architecture is based on the industry-standard 87C52 and executes the standard 8051 instruction set. The core is an accumula-
tor-based architecture using internal registers for data storage and peripheral control. This section provides a brief description of each
architecture feature. Details concerning the programming model, instruction set, and register description are provided in Section 4.
ALU
The ALU is responsible for math functions, comparisons, and general decision making. The ALU is not used explicitly by software.
Instruction decoding prepares the ALU automatically and passes it the appropriate data. The ALU primarily uses two special-function
registers (SFRs) as the source and destination for all operations. These are the accumulator and B register. The ALU also provides sta-
tus information in the program status register. The SFRs are described in the following pages.
Special-Function Registers
All peripherals and operations that are not explicitly controlled by instructions are controlled through SFRs. All SFRs are described in
Section 4. The most commonly used registers that are basic to the architecture are also described in the following pages.
Accumulator
The accumulator is a source and destination for many operations involving math, data movement, and decisions. Although it can be
bypassed, most high-speed instructions require the use of the accumulator (A or ACC) as one argument.
B Register
The B register is used as the second 8-bit argument in multiply and divide operations. When not used for these purposes, the B reg-
ister can be used as a general-purpose register.
Program Status Word
The program status word holds a selection of bit flags that include the carry flag, auxiliary carry flag, general-purpose flag, register
bank select, overflow flag, and parity flag.
Data Pointer(s)
The data pointers (DPTR and DPTR1) are used to assign a memory address for the MOVX instructions. This address can point to a
data memory location, either on- or off-chip, or a memory-mapped peripheral. When moving data from one memory area to another or
from memory to a memory-mapped peripheral, a pointer is needed for both the source and destination. The user can select the active
pointer through a dedicated SFR bit (Sel = DPS.0), or can activate an automatic toggling feature for altering the pointer selection (TSL
= DPS.5). An additional feature, if selected, provides automatic incrementing or decrementing of the current DPTR.
Stack Pointer
The stack pointer denotes the register location at the top of the stack, which is the last used value. The user can place the stack any-
where in the scratchpad RAM by setting the stack pointer to the desired location, although the lower bytes are normally used for work-
ing registers.
I/O Ports
Four 8-bit I/O ports are available. Each I/O port is represented by an SFR location, and can be written or read. The I/O port has a latch
that contains the value written by software. In general, software reads the state of external pins during a read operation.
Timer/Counters
Three 16-bit timer/counters are available. Each timer is contained in two SFR locations that can be written or read by software. The
timers are controlled by other SFRs described in Section 4.
UARTs
The two UARTs are controlled and accessed by SFRs. Each UART has an address that is used to read and write the UART. The same
address is used for both read and write operations, which are distinguished by the instruction. Each UART is controlled by its own SFR
control register.
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