Maxim Integrated Ultra-High-Speed Flash Microcontroller - Manual (Page 97)

7-5
A typical application of the PFI is to place the device into a “safe mode” when a power loss appears imminent. When the interrupt
occurs, the code vectors to location 33h. At this time, software can disable the interrupt, save any critical data, clear PFI, and then con-
tinually poll the status of the power supply through the PFI flag. As long as PFI is set, power is still below V PFW . If power returns to the
proper level, PFI is not set once cleared by software. This indicates a safe operating condition. If power continues to fall, a power-fail
reset is invoked automatically.
Power-Fail Reset
The power-fail reset automatically invokes a reset when V
CC
drops below V
RST
. This halts device operation and places all outputs in
their reset state. This state continues to be held until V
CC
drops below the voltage necessary to power the port pins. Because V
RST
is
lower than V
PFW
, the microcontroller has the option to use the power-fail interrupt to place the device into a “safe” state before the
device halts operation with a power-fail reset. The power-fail reset function cannot be disabled.
Power-On Reset
When V
CC
is applied to a system, the device holds itself in reset until power is within tolerance and stable. The internal bandgap ref-
erence provides a highly accurate and stable means of detecting power-supply levels. It requires no external circuits to accomplish
this. As power rises, the processor stays in a reset state until V
CC
> V
RST
. As V
CC
rises above VRST, internal analog circuits detect
this and activate the on-chip crystal oscillator. On-chip hardware then counts 65536 oscillator clocks. During this count, V
CC
must
remain above V
RST
or the process restarts. If an off-chip clock source is used, clock counting still begins once V
CC
> V
RST
. This count
period is used to make certain that power is within tolerance and that the oscillator has time to stabilize. This provides a very controlled
and predictable startup condition.
Once the 65536 count period has elapsed, the reset condition is removed automatically and software execution begins at the reset
vector location of 0000h. Software is able to detect the power-on reset condition using the power-on reset (POR) flag. POR is located
at WDCON.6. This bit is high to indicate that a power-on reset has occurred. It should then be cleared by software.
The complete power cycle operation is shown in Figure 7-1. Note that the interrupt threshold is fixed, but the interrupt itself is option-
al. Reset thresholds are also fixed and the reset operation is transparent. It requires no external components and no action by software
to control reset operation.
Bandgap Select
The bandgap is normally disabled automatically upon entering stop mode to provide the lowest power state. Since the bandgap is
inactive, there can be no power-fail interrupt and no power-fail reset, similar to a traditional 8051.
If the use of the power-fail features is desired in stop mode, the BGS bit (EXIF, 91h) can be used. When set to a logic 1 by software,
the bandgap reference and associated power monitor circuits remain active in stop mode. The price of this feature is higher power-
supply current requirements. In stop mode with the bandgap reference disabled (default), the processor draws approximately 10µA.
With the bandgap enabled, it draws approximately 75µA.
BGS allows the user to decide whether the control circuitry and its associated power consumption are needed. If the application is
such that power does not fail while in stop, or if it does not matter that power fails, the BGS should be set to 0 (default). If power can
fail at any time and cause problems, the BGS should be set to 1.
Watchdog Wake-Up From Idle
The watchdog wake-up is more of an application than a feature. It allows a system to enter the idle mode for power savings, then to
wake up periodically to sample the external world. Idle mode is a low-power state described below. Any of the programmable timers
can perform this function, but the watchdog allows a much longer period to be selected. At 33MHz, the maximum watchdog timeout
is over 2s. This contrasts with 23.8ms using the 16-bit timers. Software that uses the watchdog as a wake-up alarm should enable only
the watchdog interrupt and not the reset. Note that the watchdog cannot be used to wake the system while in stop mode since no
clocks are running. Stop mode is described in the Power Management Summary section.
Ultra-High-Speed Flash
Microcontroller User’s Guide
Maxim Integrated