Maxim Integrated Ultra-High-Speed Flash Microcontroller - Manual (Page 83)

6-16
Ultra-High-Speed Flash
Microcontroller User’s Guide
Figures 6-11 to 6-22 illustrate the external data memory timing for the nonpage and page mode external bus structures.
Nonpage Mode Data Memory Timing
Figure 6-11 shows execution of the MOVX instruction from internal program memory with stretch value = 0 assigned (MD2:0 = 000b).
Note that the internal memory cycles consist of one system clock while the external memory cycles always consist of four system clocks.
Figure 6-12 illustrates the same MOVX instruction with a default stretch value (MD2:0 = 001b). The stretch cycle (four system clocks)
is distributed as follows: one system clock added for address setup, two system clocks being added to the RD or WR pulse duration,
and one system clock added for address/data hold. For subsequent stretch values of 2 or 3, the full stretch cycle is added to the dura-
tion of the RD or WR pulse.
SYSCLK
ALE
PSEN
PORT2 MOVX MSB
LSB
MOVX INST INSTRUCTIONS
DATA PORT0
WR/RD
MOVX
DATA ACCESS
SYSCLK
ALE
PSEN
PORT2
PORT0
WR/RD
MOVX INST INSTRUCTIONS
MOVX DATA ACCESS
(1 STRETCH CYCLE)
= STRETCH CYCLE
MOVX MSB
MOVX DATA MOVX LSB
Figure 6-12. Nonpage Mode: MOVX (Three Cycles)
Figure 6-11. Nonpage Mode: MOVX (Two Cycles)
Maxim Integrated