Maxim Integrated Ultra-High-Speed Flash Microcontroller - Manual (Page 39)

4-31
Table 4-18. Data Memory Access
DME1 DME0
DATA MEMORY
ADDRESS
RANGE
MEMORY ACCESS
0 0 0000h–FFFFh External Data Memory (default)
X 1
0000h–03FFh
0400h–FFFFh
Internal SRAM Data Memory
External Data Memory
1 0 Reserved Reserved
SWB
Bit 5
CTM
Bit 4
4X/ 2X
Bit 3
ALEON
Bit 2
DME1, DME0
Bits 1, 0
Switchback Enable. This bit allows an enabled external interrupt or serial port activity to force the
clock divide control bits to the divide-by-1 state (01b). Upon acknowledgement of an external inter-
rupt source, the device switches modes in order to service the interrupt. Note that this means that
an external interrupt must actually be recognized (i.e., be enabled and not masked by higher pri-
ority interrupts) for the switchback to occur. For serial port reception, the switch occurs at the start
of the instructions following the falling edge of the start bit.
Crystal Multiplier Enable. This bit enables (= 1) or disables (= 0) the crystal multiplier function.
When set (= 1), the CKRY bit (EXIF.3) is cleared and the multiplier circuitry begins a stabilization
warm-up period to provide the clock multiplication factor specified by the 4X/2X bit (PMR.3). Upon
completion of the warm-up delay, the CKRY bit is set and the user can then modify CD1,CD0
(PMR.7, PMR.6) to select the crystal multiplier clock output. When clear (= 0), the crystal multipler
circuitry is disabled to conserve power. The CTM bit cannot be changed unless CD1,CD0 = 10b
and RGMD (EXIF.2) is cleared to 0. This bit is automatically cleared to 0 when the processor enters
stop mode.
Clock Multiplier Selection. This bit selects the clock multiplication factor as shown. 4X/2X = 0.
The frequency multiplier is set to two times the incoming clock by 4X/2X = 0. 4X/2X = 1 sets the
frequency multiplier to 4 times the incoming clock. This bit can only be altered when the crystal
multiplier enable bit (CTM) is cleared. Therefore, it must be set for the desired multiplication factor
prior to setting the CTM bit.
ALE Enable. When set (= 1), this bit enables the ALE signal output during on-chip program and
data memory accesses. When clear (= 0), the ALE signal output is disabled during on-chip program
and data memory accesses. External memory access automatically enables ALE independent of
the state of ALEON.
Data Memory Enable 1-0. These bits determine the functional relationship of the first 1024 bytes
of data memory. Two memory configurations are supported to allow either external data memory
access through the expanded bus of port 0 and port 2, or internal SRAM data memory access.
Note these bits are cleared after a reset, so access to the internal SRAM is prohibited until these
bits are modified.
Table 4-17. Serial Port Operation (in Oscillator Clocks)
CLOCK (MODE 0) CLOCK (MODE 2)
4X/2X CD1:0
SM2 = 0 SM2 = 1 SMOD = 0 SMOD = 1
1 00 3 1 64 32
0 00 6 2 64 32
X 01 12 4 64 32
X 10 12 4 64 32
X 11 3072 1024 16384 8192
Ultra-High-Speed Flash
Microcontroller User’s Guide
Maxim Integrated