ADLINK USB-7250 - Manual (Page 40)

30 Operations
In the USB-7230/7250, the COS detection circuit is applied to all
DI channels, with the channel(s) to enable COS detection select-
able by software. When an enabled channel changes logic level,
the COS detection circuit generates an interrupt request to the
USB microcontroller, which, when detected, latches corresponding
DI data into the COS latch register. In COS architecture, DI data is
sampled by a 48 MHz base clock, such that pulse width of the dig-
ital input exceeds 21 ns, or the COS latch register cannot latch the
correct input data. The COS latch register is cleared when the reg-
ister is read out, resuming availability to latch the susequent COS.
Figure 3-5: COS Detection Architecture
NOTE: NOTE:
Maximum frequency of COS detection depends on software
latency and computer performance, and is not guaranteed if
COS frequency exceeds 1 kHz.
Digital
Filter
0~7
USB
Bridge
CPLD
INT
USB
BUS
Digital
Filter
8~15
DI0-DI7 DI0-DI7
DI8-DI15 DI8-DI15