ADLINK USB-7250 - Manual (Page 42)

32 Operations
counter1 with falling-edge polarity. Counter value is updated and
reset in every period.
Figure 3-8: Frequency Counter Example
Since the signals are sampled by a 48MHz base clock, latch tim-
ing can generate measurement error, maximum error ratio vs.
input frequency is as follows.
CLK
CNT0
Polarity
CNT0
CNT0
FREQ
1 2 3 46 47 48 1
Freq = 1 MHz
CNT1
Polarity
CNT1
CNT1
FREQ
1 24 1
Freq = 500 KHz
24 1