ADLINK PCIe-9529 - Manual (Page 19)

Introduction 9
PCIe-9529
1.3.2 Timebase
Table 1-1: Timebase
1.3.3 Triggers
Table 1-2: Trigger Source & Mode
Table 1-3: Digital Trigger Input
1.3.4 General Specifications
Sampling Clock
Sampling Clock
Timebase
Internal: onboard synthesizer (10 MHz, accuracy
< ± 25ppm)
External: SSI
Delay Trigger Timebase PCIe clock (125 MHz)
Trigger Source & Mode
Trigger source Software, external digital trigger, analog trigger, and SSI
Trigger mode Post trigger and delay trigger
Digital Trigger Input
Sources
Front panel SMB connector
Compatibility 3.3 V TTL, 5 V tolerant
Input high threshold 2.0 V
Input low threshold (VIL) 0.8 V
Maximum input overload -0.5 V to +5.5 V
Trigger polarity
Rising or falling edge
Pulse width 20 ns minimum
Physical
Physical dimensions
167.64W x 106.68H mm (6.53 x 4.16 in)
Bus
Bus interface PCI Express x 4
Environmental Tolerance