ADLINK PCIe-9529 - Manual (Page 36)

26 Operations
specified by a 32-bit counter value with the counter clocking
based on the PCIe clock. Accordingly, maximum delay time is
the period of PCIe_CLK X (2^32 - 1) and minimum is the period
of PCIe_CLK (8 ns).
Figure 3-7: Delay Trigger Mode Acquisition
Post-Trigger or Delay-Trigger Acquisition with Re-Trigger
Post-trigger or delay trigger acquisition with re-trigger function
enables collection of data after several trigger events, as
shown. When the number of triggers is defined, the PCIe-9529
acquires specific sample data each time a trigger is accepted.
All sampled data is stored in onboard memory first, until all trig-
ger events have occurred, such that time between the previous
sampled data and the subsequent trigger event can be only
one clock period of PCIe CLK. After the initial setup, no addi-
tional software intervention is required.
Figure 3-8: Re-Trigger Mode Acquisition
Time
Operation
start
Trigger
Data
1st Trigger Event Occurs
N samples N samples
2nd Trigger Event Occurs