ADLINK HSL-AI16AO2-M-VV/-AV - Manual (Page 16)

Introducing HSL 3
Time-deterministic scanning
The HSL master controller implements a deterministic time
period when scanning all slave I/O modules. The total scanning
cycle time is exactly proportional to the number of slave
indexes. At 6 Mbps, every 30.33 µs is added for another slave
index. For an HSL system with 30 discrete I/O slave modules
(where every discrete I/O module occupies one slave index),
the scanning time period is precisely 30 X 30.33 µs = 909.9 µs.
The scan time unit based on transmission rate is illustrated
below.
Convenient wiring
The HSL master controller connects to all slave I/O modules
using Ethernet cables. This dramatically reduces the wiring
costs and effort. With Ethernet cables, hundreds or even thou-
sands of I/O data can transmitted between the HSL master and
slave I/O modules. The HSL wiring is the easiest and most
cost-effective solution to date. For low profile series, you can
make the connection by direct wiring.
Multiple I/O points
The PCI-7853 offers one HSL master controller while the PCI-
7854 offers two HSL master controllers. For maximum installa-
tion, users can have eight PCI-7853 and PCI-7854 in one sys-
tem. That means users can have 1512 slave indexes in HSL
network system. If choosing all connected modules as HSL-
DI16DO16-DB-NN, a total of 24,192 digital input and 24,192
digital output points are supported. For embedded solution,
users can choose the PMC-7852/G.
Easy I/O expansion
Expanding I/O points for centralized configuration requires
more I/O boards and available PCI or ISA slots. Problems
occur when system needs more I/O points while there are no
3 Mbps 6 Mbps 12 Mbps
Full Duplex 60.67 µs 30.33 µs 15.17 µs
Half Duplex 118 µs 59 µs 29.5 µs