ADLINK cPCI-3965 - Manual (Page 26)

12 Functional Description
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L1 Cache to Cache (C2C) transfer
X
Streaming SIMD Extensions 2 (SSE2), Streaming SIMD
Extensions 3 (SSE3) and Supplemental Streaming SIMD
Extensions 3 (SSSE3)
X
800-MHz Source-Synchronous Front Side Bus (FSB)
X
Advanced power management features including Enhanced Intel
SpeedStep® Technology and Dynamic FSB frequency switching.
X
Intel Enhanced Deeper Sleep state with P_LVL5 I/O support
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Digital Thermal Sensor (DTS)
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Intel® 64 Technology
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Enhanced Intel® Virtualization Technology
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Intel® Dynamic Acceleration Technology
X
Enhanced Multi Threaded Thermal Management (EMTTM)
X
Execute Disable Bit support for enhanced security
Intel® Celeron® Processor 550
The following list provides some of the key features of this processor:
X
Single core
X
On-die, primary 32-KB instruction cache and 32-KB
write-back data cache
X
On-die, 1-MB second level shared cache with advanced
transfer cache architecture
X
533-MHz source-synchronous front side bus (FSB)
X
Supports Intel® architecture with dynamic execution
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Data prefetch logic
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Micro-FCPGA packaging technology
X
MMX™ technology, Streaming SIMD Extensions (SSE),
Streaming SIMD Extensions 2 (SSE2), Streaming SIMD
Extensions 3 (SSE3), and Supplemental Streaming SIMD
Extensions 3 (SSSE 3)
X
Digital Thermal Sensor (DTS)
X
Execute Disable Bit support for enhanced security
X
Intel® 64 architecture (formerly Intel® EM64T)
X
Architectural and performance enhancements of the Core
microarchitecture