Altera ALTDLL - Manual (Page 58)

Chapter 4: Functional Description 4–22
DQS_CONFIG / IO_CONFIG Block
© February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide
DQS_CONFIG / IO_CONFIG Block
The DQS_CONFIG and IO_CONFIG blocks dynamically change the settings of various
configuration bits. One IO_CONFIG block is configured per I/O, whereas one
DQS_CONFIG block is configured per x4 group of I/Os (similar to
IO_CLOCK_DIVIDERs ). These blocks share the datain , clk , and update signals
eventhough they have individual enable signals.
When dynamic delay chains are enabled, two key blocks are used together with the
I/O buffer block (input buffer, output buffer, or bidirectional buffer), the I/O config
block and the delay chain block.
The IO_CONFIG block controls the configuration of the necessary delay settings. The
necessary delay settings are set into the respective delay chain block (D1, D5, and D6).
These delay settings delay data that passes through the delay chain before going
through the I/O buffer block.
The ALTDQ_DQS megafunction allows you to control the delay chain using the
following I/O config signals:
■ config_datain
■ config_clk
■ config_update
■ <xxx> _io_config_ena . <xxx> depends on which I/O pin is controlled—input,
output, bidirectional, DQS, or DQSn I/O.
f For more information about the DQS block or the DQSn I/O block and the sequence
of the shift registers, refer to the I/O Configuration Block and DQS Configuration Block
section in
Chapter 7: External Memory Interfaces in Stratix IV Devices of the Stratix IV
Devices Handbook.
f For more information about these ports, refer to the “DQS_CONFIG/IO_CONFIG
Megafunction Ports” on page 4–45 .
Configuring Dynamic Delay Chains Using the IO_CONFIG Block
The IO_CONFIG block serially shifts the value of config_datain only when
<xxx> _io_config_ena is asserted, during which you shift in the value of
config_datain to a shift register. Because a 11-bit shift register is used in the
IO_CONFIG block, you must hold <xxx> _io_config_ena asserted for 11
configuration clock cycles ( config_clk ). When the shift registers are fully loaded,
the shift register has its bits arranged in correspondence with the values for datain :
■ datain values set during the first four configuration clock cycles corresponds to
the 4–bit input delay chain values (D1).
■ datain values set during the next three configuration clock cycles corresponds to
the 3–bit output delay chain values (D6).
■ datain values set during the last four configuration clock cycles corresponds to
the 4–bit output delay chain values (D5).