Altera ALTDLL - Manual (Page 9)

2–3 Chapter 2: Getting Started
Design Flow
ALTDLL and ALTDQ_DQS Megafunctions User Guide © February 2012 Altera Corporation
Simulate the Design
After instantiating the megafunctions, the Quartus II software generates design
source files and Verilog or VHDL simulation model files. Simulate these files in
Modelsim-AE, Modelsim SE, or other third-party functional simulator tools.
f For information about functional and gate-level timing simulations, refer to
Simulating Altera Designs chapter in volume 3 of the Quartus II Handbook.
Create Timing Constraints
The ALTDLL and ALTDQ_DQS megafunctions do not provide automatic timing
scripts for custom external memory interfaces. You must create your own timing
constraints for the following paths and clocks:
■ Timing paths from FPGA I/O to external device.
■ Timing paths from I/O registers to core logic.
■ PLL and other clock constraints.
After creating your constraints, perform the timing analysis using the TimeQuest
timing analyzer in the Quartus II software.
f
Because the timing analysis for custom external memory interfaces are the same as the
timing analysis for source-synchronous interfaces, refer to the
Timing Analysis section
in volume 3 of the Quartus II Handbook and AN 433: Constraining and Analyzing
Source-Synchronous Interfaces .
The ALTDLL and ALTDQ_DQS custom PHY solution supports timing analysis using
the TimeQuest timing analyzer with Synopsys Design Constraints (SDC)
assignments. You can derive the timing constraints from the external device data
sheet and tolerances from the board layout.
f For more information about timing constraints, refer to “Appendix D: Interface
Timing Analysis” section in
AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II
GX, and Arria GX Devices .
For more information about creating timing constraints in SDC format for the
TimeQuest timing analyzer, refer to the
The Quartus II TimeQuest Timing Analyzer
chapter of the Quartus II Handbook. Depending on which simulation tool you are
using, refer to the appropriate chapter in the
Simulation section in volume 3 of the
Quartus II Handbook.
Compile the Design and Verify Timing
After constraining your design, compile your design in the Quartus II software to
generate timing reports to verify whether timing has been met.
After compiling your design in the Quartus II software, run the verifying timing
script to produce the timing report for different paths, such as write data, read data,
address and command, and core (entire interface) timing paths in your design.