Altera Phase-Locked Loop Reconfiguration IP Core - Manual (Page 39)

Specifications Page 39
Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporation
scan_chain:string := "UNUSED";
scan_init_file:string := "UNUSED";
use_scanclk_sync_register:string := "NO";
lpm_hint:string := "UNUSED";
lpm_type:string := "altpll_reconfig"
);
port(
busy: out std_logic;
clock: in std_logic;
counter_param:in std_logic_vector(2 downto 0) := (others =>
'0');
counter_type:in std_logic_vector(3 downto 0) := (others =>
'0');
data_in:in std_logic_vector(8 downto 0) := (others => '0');
data_out:out std_logic_vector(8 downto 0);
pll_areset:out std_logic;
pll_areset_in:in std_logic := '0';
pll_configupdate:out std_logic;
pll_scanaclr:out std_logic;
pll_scanclk:out std_logic;
pll_scanclkena:out std_logic;
pll_scandata:out std_logic;
pll_scandataout:in std_logic := '0';
pll_scandone:in std_logic := '0';
pll_scanread:out std_logic;
pll_scanwrite:out std_logic;
read_param:in std_logic := '0';
reconfig:in std_logic := '0';
reset: in std_logic;
reset_rom_address:in std_logic := '0';
rom_address_out:out std_logic_vector(7 downto 0);
rom_data_in:in std_logic := '0';
write_from_rom:in std_logic := '0';
write_param:in std_logic := '0';
write_rom_ena:out std_logic
);
end component;