Altera HardCopy II Clock Uncertainty Calculator - Manual (Page 35)

Altera Corporation A–3
HardCopy II Clock Uncertainty Calculator User Guide
Intra-Clock
Domain without
PLL This section provides clock transfer examples for an intra-clock domain
without a PLL.
Figure A–3 shows an example of a clock-pair = CLK1 to CLK1
Figure A–3. Intra-Clock Domain without a PLL
Table A–3 shows input of the PLL index for Figure A–3 , with respect to
the source and destination clocks.
1 If no PLL exists, enter “ 0” for both the source and destination
clocks.
INBUF
CLK1
CLK1
Source
Clock
Destination
Clock
Source
Register
Destination
Register
Table A–3. Location of Input PLLs
Source Clock Destination Clock
1st PLL 2nd PLL 1st PLL 2nd PLL
0 — 0 —