Altera HardCopy II Clock Uncertainty Calculator User Manual
Page 52
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A–20
Altera
Corporation
HardCopy II Clock Uncertainty Calculator User Guide
Inter-Clock Domain with Cascaded PLLs
shows an example of a clock-pair = CLK8 to CLK11
Figure A–21. Inter-Clock Domain with Cascaded PLLs on the Destination Clock and One PLL on the Source
Clock
shows input of the PLL index for
, with respect to
the source and destination clocks.
INBUF
CLK8
Source
Clock
Destination
Clock
Source
Register
Destination
Register
PLL3
PLL9
PLL7
CLK10
CLK10
CLK6
Table A–21. Location of Input PLLs
Source Clock
Destination Clock
1st PLL
2nd PLL
1st PLL
2nd PLL
3
—
9
7
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