Altera Stratix V Advanced Systems Development Board - Manual (Page 60)

2–50 Chapter 2: Board Components
Memory
Stratix V Advanced Systems Development Board January 2014 Altera Corporation
Reference Manual
F3 DQS_P0
Differential 1.5-V
SSTL Class I
BC25 L27 Data strobe
G3 DQS_N0
Differential 1.5-V
SSTL Class I
BD25 K27 Data strobe
C7 DQS_P1
Differential 1.5-V
SSTL Class I
AG21 C25 Data strobe
B7 DQS_N1
Differential 1.5-V
SSTL Class I
AH21 C24 Data strobe
F3 DQS_P2
Differential 1.5-V
SSTL Class I
BA25 R24 Data strobe
G3 DQS_N2
Differential 1.5-V
SSTL Class I
BB26 P24 Data strobe
C7 DQS_P3
Differential 1.5-V
SSTL Class I
AR23 K26 Data strobe
B7 DQS_N3
Differential 1.5-V
SSTL Class I
AT23 K25 Data strobe
K1 ODT 1.5-V SSTL Class I AK20 H29 On-die termination enable
J3 RASN 1.5-V SSTL Class I AR20 J28 Row address strobe
T2 RESETN 1.5-V SSTL Class I AR24 A29 Reset
L3 WEN 1.5-V SSTL Class I AY22 P26 Write enable
L8 ZQ01 — — — ZQ impedance calibration
L8 ZQ02 — — — ZQ impedance calibration
DDR3F_ / DDR3H_ (x64 bit interface) DDR3F DDR3H
N3 A0 1.5-V SSTL Class I AP31 E18 Address bus
P7 A1 1.5-V SSTL Class I AR31 E17 Address bus
P3 A2 1.5-V SSTL Class I AM31 H17 Address bus
N2 A3 1.5-V SSTL Class I AE34 M18 Address bus
P8 A4 1.5-V SSTL Class I AF32 C18 Address bus
P2 A5 1.5-V SSTL Class I AD33 P17 Address bus
R8 A6 1.5-V SSTL Class I AF31 A17 Address bus
R2 A7 1.5-V SSTL Class I AG32 R18 Address bus
T8 A8 1.5-V SSTL Class I AE29 A19 Address bus
R3 A9 1.5-V SSTL Class I AJ33 B17 Address bus
L7 A10 1.5-V SSTL Class I AN31 H19 Address bus
R7 A11 1.5-V SSTL Class I AK32 D18 Address bus
N7 A12 1.5-V SSTL Class I AR32 G17 Address bus
T3 A13 1.5-V SSTL Class I AJ32 B19 Address bus
M2 BA0 1.5-V SSTL Class I AE33 M17 Bank address bus
N8 BA1 1.5-V SSTL Class I AH33 N17 Bank address bus
M3 BA2 1.5-V SSTL Class I AM32 F17 Bank address bus
Table 2–24. FPGA2 DDR3 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 6)
Board
Reference
Schematic
Signal Name
I/O Standard Stratix V GX FPGA2 Device Pin Number Description