Altera Stratix V Advanced Systems Development Board - Manual (Page 7)

Chapter 1: Overview 1–3
Development Board Component Blocks
January 2014 Altera Corporation Stratix V Advanced Systems Development Board
Reference Manual
Dual FPGA
The development board includes two Stratix V GX FPGA devices that connect to
other components on the board to provide a better transceiver and bandwidth design
solution.
FPGA1
The first Stratix V GX FPGA device (FPGA1) connects to the following components:
■ Communication interfaces
■ One Gen3 PCI Express x8 edge connector to PLX PEX8747 switch
■ One FPGA Mezzanine Card (FMC) port
■ Memory interfaces
■ DDR3 SDRAM
■ Two 1024-MByte (MB) interfaces with 64-bit data bus
■ Two 512-MB interfaces with 32-bit data bus
■ Four 4.5-MB QDRII+ SRAM with 18-bit data bus
■ One 72-MB MoSys Bandwidth Engine IC SRAM with 16-bit data bus
(16x10.3125 G XCVR)
■ One 32-MB serial flash
■ General user I/O
■ LEDs
■ 16 user LEDs
■ Five PCI Express LEDs
■ Two FMC interface LEDs transmit/receive (TX/RX)
■ Push buttons and DIP switches
■ One CPU reset push button
■ Three general user push buttons
■ Eight general user DIP switches
FPGA2
The second Stratix V GX FPGA device (FPGA2) connects to the following
components:
■ Communication ports
■ One Gen3 PCI Express x8 edge connector to PLX PEX8747 switch
■ One universal HSMC port