Flash, Flash –63 – Altera Stratix V Advanced Systems Development Board User Manual
Page 73
Chapter 2: Board Components
2–63
Memory
January 2014
Altera Corporation
Stratix V Advanced Systems Development Board
Reference Manual
Flash
The development board supports a 1-Gb CFI-compatible synchronous flash device for
non-volatile storage of FPGA configuration data, board information, and test
application data.
The interface has a 16-bit data bus and connects to the MAX V System Controller. The
interface can sustain burst read operations at up to 52 MHz for a throughput of 832
Mbps per device. The write performance is 270 µs for a single word and 310 µs for a
32-word buffer. The erase time is 800 ms for a 128 K parameter block.
Table 2–28
lists the flash pin assignments, signal names, and functions.
Table 2–28. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)
Board
Reference (U86)
Schematic Signal Name
I/O Standard
Description
A1
FLASH_A1
1.8-V
Address bus
B1
FLASH_A2
1.8-V
Address bus
C1
FLASH_A3
1.8-V
Address bus
D1
FLASH_A4
1.8-V
Address bus
D2
FLASH_A5
1.8-V
Address bus
A2
FLASH_A6
1.8-V
Address bus
C2
FLASH_A7
1.8-V
Address bus
A3
FLASH_A8
1.8-V
Address bus
B3
FLASH_A9
1.8-V
Address bus
C3
FLASH_A10
1.8-V
Address bus
D3
FLASH_A11
1.8-V
Address bus
C4
FLASH_A12
1.8-V
Address bus
A5
FLASH_A13
1.8-V
Address bus
B5
FLASH_A14
1.8-V
Address bus
C5
FLASH_A15
1.8-V
Address bus
D7
FLASH_A16
1.8-V
Address bus
D8
FLASH_A17
1.8-V
Address bus
A7
FLASH_A18
1.8-V
Address bus
B7
FLASH_A19
1.8-V
Address bus
C7
FLASH_A20
1.8-V
Address bus
C8
FLASH_A21
1.8-V
Address bus
A8
FLASH_A22
1.8-V
Address bus
G1
FLASH_A23
1.8-V
Address bus
H8
FLASH_A24
1.8-V
Address bus
B6
FLASH_A25
1.8-V
Address bus
B8
FLASH_A26
1.8-V
Address bus
F6
FLASH_ADVN
1.8-V
Address valid
B4
FLASH_CEN
1.8-V
Chip enable
E6
FLASH_CLK
1.8-V
Clock