Document Outline

• ATCA-7370/ATCA-7370-S
• Contents
• About this Manual
  • Overview of Contents
  • Abbreviations
  • Conventions
  • Summary of Changes
• Safety Notes
  • EMC
  • Installation
  • Operation
  • SFP / SFP+ Modules
  • RJ-45 Connectors
  • Switch Settings
  • Battery
  • Environment
• Sicherheitshinweise
  • EMV
  • Installation
  • RJ-45 Stecker
  • Betrieb
  • SFP / SFP+ Modules
  • Schaltereinstellungen
  • Batterie
  • Umweltschutz
• Introduction
  • 1.1 Features
  • 1.2 Standard Compliances
  • 1.3 Mechanical Data
  • 1.4 Mechanical Layout
  • 1.5 Mean Time Between Failures
  • 1.6 Ordering Information
  • 1.7 Product Identification
• Hardware Preparation and Installation
  • 2.1 Unpacking and Inspecting the Blade
  • 2.2 Environmental and Power Requirements
    • 2.2.1 Environmental Requirements
    • 2.2.2 Power Requirements
  • 2.3 Blade layout
  • 2.4 Installing the Blade Accessories
    • 2.4.1 DIMM Memory Modules
    • 2.4.2 Cave Creek Module
  • 2.5 Installing and Removing the Blade
    • 2.5.1 Installing the Blade
    • 2.5.2 Removing the Blade
• Controls, Indicators, and Connectors
  • 3.1 Faceplate
    • 3.1.1 LEDs and Interfaces
  • 3.2 Connectors
    • 3.2.1 Faceplate Connectors
    • 3.2.2 Backplane Connectors
    • 3.2.3 Mezzanine Card Connector
    • 3.2.4 On-board Connectors
      • 3.2.4.1 Trusted Platform Module (TPM) Header
      • 3.2.4.2 FPGA JTAG Head
  • 3.3 Switch Settings
    • 3.3.1 PCH Switch
    • 3.3.2 FPGA Switch
• BIOS
  • 4.1 Features
    • 4.1.1 Update and Recovery
    • 4.1.2 DRAM Support
    • 4.1.3 Interrupt Routing
    • 4.1.4 PCI Initialization
    • 4.1.5 I/O Device Configuration
      • 4.1.5.1 Serial Ports
      • 4.1.5.2 Integrated SATA Controller
    • 4.1.6 Boot Options
      • 4.1.6.1 Boot Support for the SAS Controller
      • 4.1.6.2 Network Boot
    • 4.1.7 Console or I/O Redirection
    • 4.1.8 Serial Over LAN (SOL)
    • 4.1.9 IPMI Support
      • 4.1.9.1 Watchdogs
    • 4.1.10 SMBIOS Support
    • 4.1.11 LED Behavior During POST
    • 4.1.12 BIOS Setup Layout
      • 4.1.12.1 Board Information Display
    • 4.1.13 USB 2.0 Ports
    • 4.1.14 Supported Operating Systems
    • 4.1.15 SPI Boot Flash
    • 4.1.16 Serial Console and BIOS Printouts
      • 4.1.16.1 BIOS Printouts to DRAM
    • 4.1.17 BIOS Interface towards OS
      • 4.1.17.1 Proprietary BIOS Data Area (BDA) Bytes
      • 4.1.17.2 BIOS CLI Tool - IPMIBPAR
  • 4.2 Setup Utility
    • 4.2.1 Main Menu
    • 4.2.2 Advanced Menu
      • 4.2.2.1 Boot Configuration
      • 4.2.2.2 Processor Configuration
      • 4.2.2.3 Peripheral Configuration
      • 4.2.2.4 HDD Configuration
      • 4.2.2.5 Memory Configuration
      • 4.2.2.6 South Bridge Configuration
      • 4.2.2.7 SMBIOS Event Log
    • 4.2.3 Security Menu
    • 4.2.4 Boot Menu
    • 4.2.5 Save and Exit Menu
• Functional Description
  • 5.1 Block Diagram
  • 5.2 Processor
  • 5.3 Memory
    • 5.3.1 DDR3 Main Memory
  • 5.4 Platform Controller Hub (PCH)
  • 5.5 PCH I/O Controller
  • 5.6 Ethernet Ports
    • 5.6.1 ATCA 3.0 Base Interface
    • 5.6.2 Fabric Interface ATCA 3.1
    • 5.6.3 Faceplate Ethernet Ports
    • 5.6.4 Update Channel Ethernet
  • 5.7 Storage
  • 5.8 IPMC
  • 5.9 Serial Redirection
  • 5.10 Real Time Clock
  • 5.11 Serial ATA
  • 5.12 IPMI Over LAN
  • 5.13 USB 2.0 Interface
  • 5.14 SMBus Connections
  • 5.15 Glue Logic FPGA
• Maps and Registers
  • 6.1 Interrupt Structure
    • 6.1.1 PIC (Non-APIC) D31:F0 Interrupt Mapping
    • 6.1.2 APIC (D31:F0) Interrupt Mapping
    • 6.1.3 Non-Maskable Interrupt Generation
  • 6.2 Registers
    • 6.2.1 Register Decoding
      • 6.2.1.1 LPC Decoding
      • 6.2.1.2 SPI Register Decoding
    • 6.2.2 POST Code Register
    • 6.2.3 Super IO Configuration Register
      • 6.2.3.1 Entering the Configuration State
      • 6.2.3.2 Exiting the Configuration State
      • 6.2.3.3 Configuration Mode
      • 6.2.3.4 Super I/O Configuration Registers
    • 6.2.4 UART1 and UART2 Register Map
      • 6.2.4.1 UART Register Overview
    • 6.2.5 UART Registers DLAB=0
      • 6.2.5.1 Receiver Buffer Register (RBR)
      • 6.2.5.2 Transmitter Holding Register (THR)
      • 6.2.5.3 Interrupt Enable Register (IER)
      • 6.2.5.4 Interrupt Identification Register (IIR)
      • 6.2.5.5 FIFO Control Register (FCR)
      • 6.2.5.6 Line Control Register (LCR)
      • 6.2.5.7 Modem Control Register (MCR)
      • 6.2.5.8 Line Status Register (LSR)
      • 6.2.5.9 Modem Status Register (MSR)
      • 6.2.5.10 Scratch Register (SCR)
    • 6.2.6 Programmable Baud Rate Generator
  • 6.3 FPGA Register Mapping
    • 6.3.1 LPC I/O Register Map
    • 6.3.2 IPMC SPI Register Map
    • 6.3.3 Module Identification Register
    • 6.3.4 Version Register
    • 6.3.5 Serial Redirection Console Register
    • 6.3.6 SOL Control Register
    • 6.3.7 Serial Routing Register
    • 6.3.8 IPMC Power Level Register
    • 6.3.9 Payload Power Control Register
    • 6.3.10 I2C Switch Control Register
    • 6.3.11 Payload Power-Button Register
    • 6.3.12 Reset Registers
      • 6.3.12.1 Reset Mask Register
      • 6.3.12.2 Reset Function Register
      • 6.3.12.3 IPMC Reset Payload Request Register
      • 6.3.12.4 BIOS Reset Payload Request Register
      • 6.3.12.5 OS Reset Payload Request Register
      • 6.3.12.6 Payload Reset Source for IPMC Register
      • 6.3.12.7 Payload Reset Source for BIOS Register
      • 6.3.12.8 Payload Reset Source for OS Register
      • 6.3.12.9 IPMC Watchdog Timeout Register
      • 6.3.12.10 IPMC Watchdog Timeout for BIOS Register
      • 6.3.12.11 IPMC Watchdog Timeout for OS Register
      • 6.3.12.12 FPGA-Payload-Watchdog Threshold Register
      • 6.3.12.13 FPGA Payload Watchdog Clear Register
      • 6.3.12.14 FPGA-IPMC-Watchdog Threshold Register
    • 6.3.13 Flash Control Register
    • 6.3.14 RTM Status and Control Register
    • 6.3.15 Blue LED Status and Control Register
    • 6.3.16 User LED Status and Control Register
    • 6.3.17 Miscellaneous Status and Control Register
    • 6.3.18 Debug Switch and LED Status Register
    • 6.3.19 Scratch Register
    • 6.3.20 POST Code Register
  • 6.4 Standard Status Codes
• Serial Over LAN
  • 7.1 Overview
  • 7.2 Installing the ipmitool
  • 7.3 Configuring SOL Parameters
    • 7.3.1 Using Standard IPMI Commands
    • 7.3.2 Using ipmitool
  • 7.4 Establishing a SOL Session
• Supported IPMI Commands
  • 8.1 Standard IPMI Commands
    • 8.1.1 Global IPMI Commands
    • 8.1.2 System Interface Commands
    • 8.1.3 BMC Watchdog Commands
    • 8.1.4 SEL Device Commands
    • 8.1.5 FRU Inventory Commands
    • 8.1.6 Sensor Device Commands
    • 8.1.7 Chassis Device Commands
      • 8.1.7.1 System Boot Options Commands
    • 8.1.8 Event Commands
    • 8.1.9 LAN Device Commands
  • 8.2 PICMG 3.0 Commands
  • 8.3 Artesyn Embedded Technologies Specific Commands
    • 8.3.1 Set/Get Feature Configuration Commands
      • 8.3.1.1 Set Feature Configuration Command
      • 8.3.1.2 Get Feature Configuration Command
    • 8.3.2 Serial Output Commands
      • 8.3.2.1 Set Serial Output Command
      • 8.3.2.2 Get Serial Output Command
    • 8.3.3 OEM Set/Get ACPI Power Commands
      • 8.3.3.1 OEM Set ACPI Power State (0x17)
      • 8.3.3.2 OEM Get ACPI Power State (0x18)
    • 8.3.4 OEM Set/Get Performance Commands
      • 8.3.4.1 OEM Set Performance Mode (0x21)
      • 8.3.4.2 OEM Get Performance Mode (0x22)
  • 8.4 Pigeon Point Specific Commands
    • 8.4.1 Get Status Command
    • 8.4.2 Get Serial Interface Properties Command
    • 8.4.3 Set Serial Interface Properties Command
    • 8.4.4 Get Debug Level Command
    • 8.4.5 Set Debug Level Command
    • 8.4.6 Get Hardware Address Command
    • 8.4.7 Set Hardware Address Command
    • 8.4.8 Get Handle Switch Command
    • 8.4.9 Set Handle Switch Command
    • 8.4.10 Get Payload Communication Time-Out Command
    • 8.4.11 Set Payload Communication Time-Out Command
    • 8.4.12 Enable Payload Control Command
    • 8.4.13 Disable Payload Control Command
    • 8.4.14 Reset IPMC Command
    • 8.4.15 Hang IPMC Command
    • 8.4.16 Graceful Reset Command
    • 8.4.17 Get Payload Shutdown Time-Out Command
    • 8.4.18 Set Payload Shutdown Time-Out Command
    • 8.4.19 Get Module State Command
    • 8.4.20 Enable Module Site Command
    • 8.4.21 Disable Module Site Command
    • 8.4.22 Reset Carrier SDR Repository Command
• FRU Information and Sensor Data Records
  • 9.1 FRU Information
  • 9.2 Power Configuration
  • 9.3 Sensor Data Records
• Firmware Upgrade
  • 10.1 HPM.1 Firmware Upgrade
    • 10.1.1 Overview
    • 10.1.2 Installing the ipmitool
      • 10.1.2.1 Update Procedure
    • 10.1.3 Interface
      • 10.1.3.1 KCS Interface
      • 10.1.3.2 IPMB-0
      • 10.1.3.3 IPMI Over LAN (BASE)
  • 10.2 IPMC Upgrade
  • 10.3 BIOS/FPGA Update
  • 10.4 Upgrade Package
• A Troubleshooting
  • A.1 Error List
    • A.1.1 CPU Blade is Not Functioning Properly
• B Related Documentation
  • B.1 Artesyn Embedded Technologies - Embedded Computing Documentation
  • B.2 Related Specifications