3 fpga register mapping, 1 lpc i/o register map, Table 6-40 – Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (June 2014) User Manual

Page 150: Divisor latch lsb register (dll), if dlab=1, Table 6-41, Divisor latch msb register (dlm), if dlab=1, Maps and registers

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3 fpga register mapping, 1 lpc i/o register map, Table 6-40 | Divisor latch lsb register (dll), if dlab=1, Table 6-41, Divisor latch msb register (dlm), if dlab=1, Maps and registers | Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (June 2014) User Manual | Page 150 / 254 3 fpga register mapping, 1 lpc i/o register map, Table 6-40 | Divisor latch lsb register (dll), if dlab=1, Table 6-41, Divisor latch msb register (dlm), if dlab=1, Maps and registers | Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (June 2014) User Manual | Page 150 / 254
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