Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (June 2014) - Manual (Page 156)

Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54F) 156
6.3.8 IPMC Power Level Register
7:2 Reserved 0 r
Table 6-47 Serial Routing Register
Address Offset: 0x05
Bit Description Default Access
When bit1 in this register is 0, FPGA_COM_SW outputs high level. When it is in 1, it outputs
to low level.
Table 6-48 IPMC Power Level Register
Address Offset: 0x06
Bit Description Default Access
7:0 IPMC Power Level. IPMC writes a value, which
represents a defined power level. 0x00 IPMC: r/w
LPC: r
Whenever the IPMC writes and data into this register, it should also produce an 8 ms negative
pulse on FPGA_PCH_GPIO5 to notify payload.