Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (June 2014) - Manual (Page 157)

Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54F) 157
6.3.9 Payload Power Control Register
6.3.10 I2C Switch Control Register
Table 6-49 Payload Power Control Register
Address Offset: 0x07
Bit Description Default Access
0 IPMC turn on payload power request:
1: Payload power on
0: Payload power off 0 IPMC: r/w
7:1 Reserved 0 r
Table 6-50 I2C Switch Control Register
Address Offset: 0x08
Bit Description Default Access
0 FPGA_SPD_MUX_S[0] 0 IPMC: r/w
LPC: r
1 FPGA_SPD_MUX_S[1] 1 IPMC: r
LPC: r/w
2 FPGA_PCH_I2C_SEL 0 IPMC: r/w
LPC: r
7:3 Reserved 0 r