Measurement Computing CIO-DAS16/M1 User Manual
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IRQ LEVEL L2, L1 & L0: Set the PC system bus IRQ level.
L2
L1
L0 SYSTEM IRQ LEVEL SELECTED
0
0
0
IRQ 10
0
0
1
IRQ 11
0
1
0
IRQ 12
0
1
1
IRQ 15
1
0
0
IRQ 2
1
0
1
IRQ 3
1
1
0
IRQ 5
1
1
1
IRQ 7
SPARE: Two spare bits, currently unused. When used, the inactive level will be 0, the active level will
be 1. Fill these bits with 0 for now.
S1, S0: Pacer source control.
S1
S0
PACER SOURCE
0
0
Start a single conversion by writing to BASE + 0
0
1
Start a single conversion by writing to BASE + 0
1
0
Externally paced conversions by pin 25 LO-HI edges
1
1
Internally paced via the counters at BASE + D and BASE + E
4.6.6
Channel Gain Queue Ad dress Register
BASE ADDRESS + 6
7
6
5
4
3
2
1
0
QA7
QA6
QA5
QA4
QA3
QA2
QA1
QA0
CHANNEL/GAIN QUEUE
The channel/gain queue is implemented with a simple 8 bit up-counter and a 256 byte memory and some
control logic. Each channel/gain (C/G) pair is loaded as one byte.
IMPORTANT NOTE: Any channel can be sampled as long as it is the only sample in the channel/gain
list. For example, sampling channel 3 repeatedly at 1Mhz is allowed. HOWEVER, when more than one
channel is in the channel gain list, these rules must be followed:
1) There must be an even number of entries in the queue.
2) Even channels must be at even queue addresses (0, 2, 4, ...)
3) Odd channels must be at odd queue addresses (1, 3, 5, ...)
NOTE: Failure to follow queue sequencing rules will result in scrambling of data between channels.
The first C/G in the scan is loaded into C/G memory address 0. The second C/G in the scan is loaded into
C/G memory address 1, and so on until the last C/G in the scan is the last item loaded into C/G memory.